Publication Type |
Journal Article |
School or College |
College of Engineering |
Department |
Computing, School of |
Creator |
Balasubramonian, Rajeev |
Other Author |
Albonesi, David; Buyuktosunoglu, Alper; Dwarkadas, Sandhya |
Title |
Dynamic memory hierarchy performance optimization |
Date |
2000 |
Description |
Although microprocessor performance continues to increase at a rapid pace, the growing processor-memory speed gap threatens to limit future performance gains. In this paper, we propose a novel configurable cache and TLB as an alternative to conventional two-level hierarchies. This organization leverages repeater insertion to provide low-cost configurability of size and speed. A novel configuration management algorithm dynamically measures hit and miss intolerance over intervals of instruction execution in order to tailor the cache and TLB organizations on-the-fly to improve memory hierarchy performance. The result is an average 14% improvement in IPC and a speedup of up to 1.55 across a broad class of applications compared to a conventional two-level hierarchy of identical total size. |
Type |
Text |
Publisher |
Workshop on Solving the Memory Wall Problem |
Subject |
Microprocessor performance; Processor-memory speed gap |
Subject LCSH |
Memory hierarchy (Computer science); Microprocessors; Cache memory |
Language |
eng |
Bibliographic Citation |
Balasubramonian, R., Albonesi, D., Buyuktosunoglu, A., & Dwarkadas, S. (2000). Dynamic memory hierarchy performance optimization. Workshop on Solving the Memory Wall Problem, held in conjunction with the 27th ISCA, Vancouver, June. |
Rights Management |
(c)Balasubramonian, R., Albonesi, D., Buyuktosunoglu, A., & Dwarkadas, S. |
Format Medium |
application/pdf |
Format Extent |
94,169 bytes |
Identifier |
ir-main,12013 |
ARK |
ark:/87278/s6086prp |
Setname |
ir_uspace |
ID |
705455 |
Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6086prp |