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Creator | Title | Description | Subject | Date |
176 |
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Mathew, Binu K.; Davis, Al; Fang, Zhen | A Gaussian probability accelerator for SPHINX 3 | Accurate real-time speech recognition is not currently possible in the mobile embedded space where the need for natural voice interfaces is clearly important. The continuous nature of speech recognition coupled with an inherently large working set creates significant cache interference with other... | Speech recognition; SPHINX 3; Speech recognizers | 2003-07-22 |
177 |
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Gardner, Reed M. | Computerized Medical Care: The HELP System at LDS Hospital | Biomedical Informatics | | 1992 |
178 |
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Lindstrom, Gary E. | Layered, server-based support for Object-Oriented application development | This paper advocates the idea that the physical modularity (file structure) of application components supported by conventional OS environments can be elevated to the level of logical modularity, which in turn can directly support application development in an object-oriented manner. We demonstrate ... | Object-Oriented application development | 1995 |
179 |
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Gardner, Reed M. | Trouble-Shooting Pressure Monitoring Systems: When do the Numbers Lie? | Biomedical Informatics | | 1987 |
180 |
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Gardner, Reed M. | Computerized Clinical Decision-Support in Respiratory Care | Biomedical Informatics | | 2004 |
181 |
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Gardner, Reed M. | Computerized Management of Intensive Care Patients | Biomedical Informatics | | 1986 |
182 |
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Balasubramonian, Rajeev | Dynamic memory hierarchy performance optimization | Although microprocessor performance continues to increase at a rapid pace, the growing processor-memory speed gap threatens to limit future performance gains. In this paper, we propose a novel configurable cache and TLB as an alternative to conventional two-level hierarchies. This organization le... | Microprocessor performance; Processor-memory speed gap | 2000 |
183 |
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Warner, Homer R. | HELP - A Hospital-Wide System for Computer-Based Support of Decision-Making | Biomedical Informatics | | 1981 |
184 |
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Brunvand, Erik L.; Carter, John | Impulse: building a smarter memory controller | Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through configurable physical address remapping. By remapping physical addresses, applications control how their data is ac... | | 1999 |
185 |
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Carter, John; Susarla, Sai R. | Khazana An infrastructure for building distributed services | Essentially all distributed systems?? applications?? and services at some level boil down to the problem of man aging distributed shared state Unfortunately?? while the problem of managing distributed shared state is shared by many applications?? there is no common means of managing the data ... | Khazana; Distributed shared state | 1998 |
186 |
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Carter, John B. | Khazana an infrastructure for building distributed services | Essentially all distributed systems, applications and service at some level boil down to the problem of managing distributed shared state. Unfortunately, while the problem of managing distributed shared state is shared by man applications, there is no common means of managing the data - every applic... | Khazana; Distributed shared state | 1998 |
187 |
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Orr, Douglas B. | OMOS - An object server for program execution | The benefits of object-oriented programming are well known, but popular operating systems provide very few object-oriented features to users, and few are implemented using object-oriented techniques themselves. In this paper we discuss a mechanism for applying object-oriented programming concepts to... | OMOS; Object server | 1992 |
188 |
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Gopalakrishnan, Ganesh | Performance analysis and optimization of asynchronous circuits | Asynchronous/Self-timed circuits are beginning to attract renewed attention as promising means of dealing with the complexity of modern VLSI designs. However, there are very few analysis techniques or tools available for estimating the performance of asynchronous circuits. In this paper we adapt th... | Asynchronous circuits; Performance analysis; Optimization; VLSI circuits | 1994 |
189 |
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Myntti, Jeremy | Personal Digital Archiving | Presentation on personal digital archiving for family history work at the RootsTech Conference, Salt Lake City, Utah. | Family history; Personal digital archiving | 2019-03-01 |
190 |
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Gardner, Reed M. | Selection and Standardization of Respiratory Monitoring Equipment | Biomedical Informatics | | 1986 |
191 |
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Brunvand, Erik L. | A comparison of modular self-timed design styles | State-machine sequencing methods in modular 2-phase and 4-phase asynchronous handshake control are compared. Design styles are discussed, and the sequencers are tested against each other using a medium-scale minicomputer test design implemented in FPGAs. Seven 4-phase sequencers are tested. In these... | Self-timed; State-machine sequencing; Asynchronous handshake control | 1995 |
192 |
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Zhang, Lixin | A comparison of online superpage promotion mechanisms | The amount of data that a typical translation lookaside buffer (TLB) can map has not kept pace with the growth in cache sizes and application footprints. As a result, the cost of handling TLB misses limits the performance of an increasing number of applications. The use of superpages, multiple adjac... | Superpages; Translation lookaside buffer; TLB | 1999 |
193 |
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Gu, Jun | An optimal, parallel discrete relaxation algorithm and architecture (Revised January 1988 and August 1989) | A variety of problems in artificial intelligence, operations research, symbolic logic, pattern recognition and computer vision, and robot manipulation are special cases of the Consistent Labeling Problem (CLP). The Discrete Relaxation Algorithm (DRA) is an efficient computational technique to enfor... | Consistent Labeling Problem; CLP; Discrete Relaxation Algorithm; DRA | 1988 |
194 |
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Davis, Al | Automating the design of embedded domain specific accelerators | Domain specific architecture (DSA) design currently involves a lengthy process that requires significant designer knowledge, experience, and time in arriving at a suitable code generator and architecture for the target application suite. Given the stringent time to market constraints and the dyna... | Domain specific architecture; Stall cycle analysis; SCA; Domain specific accelerators | 2008 |
195 |
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Gardner, Reed M. | The Computer for Charting and Monitoring | Biomedical Informatics | | 1993 |
196 |
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Warner, Homer R. | The HELP System | Biomedical Informatics | | 1984 |
197 |
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Richardson, William F.; Brunvand, Erik L. | The NSR processor prototype | The NSR Non Synchronous RISC processor is a general purpose processor structured as a collection of self timed units that operate concurrently and communicate over bundled data channels in the style of micropipelines?? These units correspond to standard synchronous pipeline stages such as Instr... | Self-timed Systems; Asynchronous systems; Micropipelines; FPGAs; RISC processor | 1992 |
198 |
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Regehr, John | Operating system support for multimedia: the programming model matters | Multimedia is an increasingly important part of the mix of applications that users run on personal computers and workstations. The requirements placed on a multimedia operating system are demanding and often conflicting: untrusted, independently written soft real-time applications must be able to co... | | 2000-01-01 |
199 |
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Freire, Juliana; Silva, Claudio T. | Querying and creating visualizations by analogy | While there have been advances in visualization systems, particularly in multi-view visualizations and visual exploration, the process of building visualizations remains a major bottleneck in data exploration. We show that provenance metadata collected during the creation of pipelines can be reused ... | Provenance; VisTrails; Pipelines; Query-by-example | 2007-11 |
200 |
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Yang, Yue; Gopalakrishnan, Ganesh; Lindstrom, Gary E. | Rigorous concurrency analysis of multithreaded programs | This paper explores the practicality of conducting program analysis for multithreaded software using constraint solv- ing. By precisely defining the underlying memory consis- tency rules in addition to the intra-thread program seman- tics, our approach orders a unique advantage for program ver- ... | Concurrency analysis; Multithreaded programs | 2003 |