Publication Type |
Journal Article |
School or College |
College of Engineering |
Department |
Computing, School of |
Creator |
Balasubramonian, Rajeev |
Other Author |
Albonesi, David; Buyuktosunoglu, Alper; Dwarkadas, Sandhya |
Title |
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures |
Date |
2000 |
Description |
Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper we propose a cache and TLB layout and design that leverages repeater insertion to provide dynamic low-cost configurability trading of size and speed on a per application phase basis. A novel configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration. When applied to a two-level cache and TLB hierarchy at O.Ipm technology, the result is an average 15% reduction in cycles per instruction (CPI), corresponding to an average 27% reduction in memory-CPI, across a broad class of applications compared to the best conventional two-level hierarchy of comparable size. Projecting to sub-. I pm technology design considerations that call for a three-level conventional cache hierarchy for performance reasons, we demonstrate that a configurable L2/L3 cache hierarchy coupled with a conventional LI results in an average 43% reduction in memory hierarchy energy in addition to improved performance. |
Type |
Text |
Publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
First Page |
245 |
Last Page |
257 |
DOI |
10.1109/MICRO.2000.898075 |
Subject |
Translation lookaside buffer (TLB) |
Subject LCSH |
Memory hierarchy (Computer science); Cache memory; Microprocessors; Computer architecture; Buffer storage (Computer science); Microprocessors -- Energy consumption |
Language |
eng |
Conference Title |
MICRO 33. 33rd Annual International Symposium on Microarchitecture; 10-13 Dec. 2000; Monterey, CA, USA |
Bibliographic Citation |
Balasubramonian, R., Albonesi, D., Buyuktosunoglu, A., & Dwarkadas, S. (2000). Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures. Proceedings of the Annual International Symposium on Microarchitecture, 245-57. |
Rights Management |
(c) 2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. http://dx.doi.org/10.1109/MICRO.2000.898075 |
Format Medium |
application/pdf |
Format Extent |
1,346,580 bytes |
Identifier |
ir-main,11486 |
ARK |
ark:/87278/s6ns1cbr |
Setname |
ir_uspace |
ID |
705095 |
Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6ns1cbr |