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76 An optimal, parallel discrete relaxation algorithm and architecture (Revised January 1988 and August 1989)A variety of problems in artificial intelligence, operations research, symbolic logic, pattern recognition and computer vision, and robot manipulation are special cases of the Consistent Labeling Problem (CLP). The Discrete Relaxation Algorithm (DRA) is an efficient computational technique to enfor...Consistent Labeling Problem; CLP; Discrete Relaxation Algorithm; DRA1988
77 Automating the design of embedded domain specific acceleratorsDomain specific architecture (DSA) design currently involves a lengthy process that requires significant designer knowledge, experience, and time in arriving at a suitable code generator and architecture for the target application suite. Given the stringent time to market constraints and the dyna...Domain specific architecture; Stall cycle analysis; SCA; Domain specific accelerators2008
78 Dynamic memory hierarchy performance optimizationAlthough microprocessor performance continues to increase at a rapid pace, the growing processor-memory speed gap threatens to limit future performance gains. In this paper, we propose a novel configurable cache and TLB as an alternative to conventional two-level hierarchies. This organization le...Microprocessor performance; Processor-memory speed gap2000
79 ETYMA: a framework for modular systemsModularity, i.e. support for the flexible construction, adaptation, and combination of units of software, is an important goal in many systems. In most cases, however, systems achieve only a few aspects of modularity. The problem can be traced to the inflexibility, or the limited view of modularity ...ETYMA; Modularity; Modular systems1994
80 Exploring power behaviors and trade-offs of in-situ data analyticsAs scientific applications target exascale, challenges related to data and energy are becoming dominating concerns. For example, coupled simulation workflows are increasingly adopting in-situ data processing and analysis techniques to address costs and overheads due to data movement and I/O. However...2013-01-01
81 Graphical man/machine communications: December 1972The object of the graphical man/machine communication effort is the development of computers and computing techniques the people may use interactively in real time to extend their problem-solving capability, and to work cooperatively by means of improved communications via computer. This report summ...Waveform processing; Symbolic computation; Man/machine communications1972-12
82 Impulse: building a smarter memory controllerImpulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through configurable physical address remapping. By remapping physical addresses, applications control how their data is ac...1999
83 Khazana An infrastructure for building distributed servicesEssentially all distributed systems?? applications?? and services at some level boil down to the problem of man aging distributed shared state Unfortunately?? while the problem of managing distributed shared state is shared by many applications?? there is no common means of managing the data ...Khazana; Distributed shared state1998
84 Khazana an infrastructure for building distributed servicesEssentially all distributed systems, applications and service at some level boil down to the problem of managing distributed shared state. Unfortunately, while the problem of managing distributed shared state is shared by man applications, there is no common means of managing the data - every applic...Khazana; Distributed shared state1998
85 Layered, server-based support for Object-Oriented application developmentThis paper advocates the idea that the physical modularity (file structure) of application components supported by conventional OS environments can be elevated to the level of logical modularity, which in turn can directly support application development in an object-oriented manner. We demonstrate ...Object-Oriented application development1995
86 Memory hierarchy reconfiguration for energy and performance in general-purpose processor architecturesConventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper we propose a cache and TLB layout and design that leverages repeater insertion to provide dynamic low-cost configurability trading of size and speed on a per application ...Translation lookaside buffer (TLB)2000
87 MP-LOCKs: Replacing hardware synchronization primitives with message passingShared memory programs guarantee the correctness of concurrent accesses to shared data using interprocessor synchronization operations. The most common synchronization operators are locks, which are traditionally implemented in user-level libraries via a mix of shared memory accesses and hardware sy...MP-LOCKs; Message passing; Shared memory programs; Synchronization operators; Synchronization primitives2011-05
88 The NSR processor prototypeThe NSR Non Synchronous RISC processor is a general purpose processor structured as a collection of self timed units that operate concurrently and communicate over bundled data channels in the style of micropipelines?? These units correspond to standard synchronous pipeline stages such as Instr...Self-timed Systems; Asynchronous systems; Micropipelines; FPGAs; RISC processor1992
89 OMOS - An object server for program executionThe benefits of object-oriented programming are well known, but popular operating systems provide very few object-oriented features to users, and few are implemented using object-oriented techniques themselves. In this paper we discuss a mechanism for applying object-oriented programming concepts to...OMOS; Object server1992
90 Operating system support for multimedia: the programming model mattersMultimedia is an increasingly important part of the mix of applications that users run on personal computers and workstations. The requirements placed on a multimedia operating system are demanding and often conflicting: untrusted, independently written soft real-time applications must be able to co...2000-01-01
91 Performance analysis and optimization of asynchronous circuitsAsynchronous/Self-timed circuits are beginning to attract renewed attention as promising means of dealing with the complexity of modern VLSI designs. However, there are very few analysis techniques or tools available for estimating the performance of asynchronous circuits. In this paper we adapt th...Asynchronous circuits; Performance analysis; Optimization; VLSI circuits1994
92 Power efficient resource scaling in partitioned architectures through dynamic heterogeneityThe ever increasing demand for high clock speeds and the desire to exploit abundant transistor budgets have resulted in alarming increases in processor power dissipation. Partitioned (or clustered) architectures have been proposed in recent years to address scalability concerns in future billion-tr...Partitioned architectures; Clustered architectures; Energy × Delay2, Temperature; Dynamic frequency scaling; Thermal emergency2006
93 Querying and creating visualizations by analogyWhile there have been advances in visualization systems, particularly in multi-view visualizations and visual exploration, the process of building visualizations remains a major bottleneck in data exploration. We show that provenance metadata collected during the creation of pipelines can be reused ...Provenance; VisTrails; Pipelines; Query-by-example2007-11
94 Rigorous concurrency analysis of multithreaded programsThis paper explores the practicality of conducting program analysis for multithreaded software using constraint solv- ing. By precisely defining the underlying memory consis- tency rules in addition to the intra-thread program seman- tics, our approach orders a unique advantage for program ver- ...Concurrency analysis; Multithreaded programs2003
95 The roll back chip: hardware support for distributed simulation using time warpDistributed simulation offers an attractive means of meeting the high computational demands of discrete event simulation programs. The Time Warp mechanism has been proposed to ensure correct sequencing of events in distributed simulation programs without blocking processes unnecessarily. However, th...Roll back chip; Distributed simulation; Discrete event; Simulation programs; Time Warp mechanism1987
96 Scheduling Tasks with mixed preemption relations for robustness to timing faultsThis paper introduces and shows how to schedule two novel scheduling abstractions that overcome limitations of existing work on preemption threshold scheduling. The abstractions are task clusters, groups of tasks that are mutually non-preemptible by design, and task barriers, which partition the tas...2002-01-01
97 Using annotated interface definitions to optimize RPCIn RPC-based communication, it is useful to distinguish the RPC interface, which is the "network contract" between the client and the server, from the presentation, which is the "programmer's contract" between the RPC stubs and the code that calls or is called by them. Presentation is usually a fixe...annotated interface definitions; RPC-based communication1995
98 VisComplete: automating suggestions for visualization pipelinesBuilding visualization and analysis pipelines is a large hurdle in the adoption of visualization and workflow systems by domain scientists. In this paper, we propose techniques to help users construct pipelines by consensus-automatically suggesting completions based on a database of previously creat...VisComplete; Workflows; Auto completion; Visualization pipelines2008-11
99 VisMashup: streamlining the creation of custom visualization applicationsVisualization is essential for understanding the increasing volumes of digital data. However, the process required to create insightful visualizations is involved and time consuming. Although several visualization tools are available, including tools with sophisticated visual interfaces, they are o...VisMashup; Dataflow; Visualization systems; Mashups; Medleys2009-11
100 A comparison of software and hardware synchronization mechanisms for distributed shared memory multiprocessorsEfficient synchronization is an essential component of parallel computing. The designers of traditional multiprocessors have included hardware support only for simple operations such as compare-and-swap and load-linked/store-conditional, while high level synchronization primitives such as locks, bar...Hardware locks1996
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