| Publication Type |
Journal Article |
| School or College |
College of Engineering |
| Department |
Computing, School of |
| Creator |
Richardson, William F. |
| Title |
The Fred VHDL Model |
| Date |
1995 |
| Description |
This is the companion document to my dissertation. It contains 47 pages of schematics, and 163 pages of VHDL code. It is pretty meaningless without the dissertation, and it only exists because I felt that I should archive this information somewhere. |
| Type |
Text |
| Publisher |
University of Utah |
| First Page |
1 |
| Last Page |
220 |
| Subject LCSH |
VHDL (Computer hardware description language); Asynchronous circuits; Timing circuits |
| Language |
eng |
| Bibliographic Citation |
Richardson, W. F. (1995). The Fred VHDL Model. 1-220. UUCS-95-021. |
| Series |
University of Utah Computer Science Technical Report |
| Relation is Part of |
Architectural considerations in a self-timed processor design; ARPANET |
| Rights Management |
©University of Utah |
| Format Medium |
application/pdf |
| Format Extent |
21,787,805 bytes |
| Identifier |
ir-main,16218 |
| ARK |
ark:/87278/s6nc6jfx |
| Setname |
ir_uspace |
| ID |
704039 |
| Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6nc6jfx |
