Publication Type |
Journal Article |
School or College |
College of Engineering |
Department |
Electrical & Computer Engineering |
Creator |
Myers, Chris J. |
Other Author |
Belluomini , Wendy |
Title |
Timed event/level structures |
Date |
1997 |
Description |
This paper presents timed event/level(TEL) structures, an extension to timed event-rule structures, which allows the general use of signal levels and timing in the specification of an asynchronous circuit. TEL structures can express true OR causality, as well as language constructs that are very difficult to describe using purely event based specification methods. This flexibility makes it possible to easily express VHDL and CSP handshaking specifications as TEL structures. Circuits can be synthesized from timed event/level structures using a modified version of the geometric timing analysis method without any significant increase in synthesis time. Therefore, timed event/level structures increase specification flexiblity without impacting synthesis performance. |
Type |
Text |
Publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
Language |
eng |
Bibliographic Citation |
Belluomini, W. J., & Myers, C. J. (1997). Timed event/level structures. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems. December. |
Rights Management |
(c) 1998 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
Format Medium |
application/pdf |
Format Extent |
117,866 bytes |
Identifier |
ir-main,15049 |
ARK |
ark:/87278/s6d79vmg |
Setname |
ir_uspace |
ID |
703570 |
Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6d79vmg |