Evaluating the potential of programmable multiprocessor cache controllers

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Publication Type technical report
School or College College of Engineering
Department Computing, School of
Creator Carter, John B.
Other Author Hibler, Mike; Kuramkote, Ravindra R.
Title Evaluating the potential of programmable multiprocessor cache controllers
Date 1994
Description The next generation of scalable parallel systems (e.g., machines by KSR, Convex, and others) will have shared memory supported in hardware, unlike most current generation machines (e.g., offerings by Intel, nCube, and Thinking Machines). However, current shared memory architectures are constrained by the fact that their cache controllers are hardwired and inflexible, which limits the range of programs that can achieve scalable performance. This observation has led a number of researchers to propose building programmable multiprocessor cache controllers that can implement a variety of caching protocols, support multiple communication paradigms, or accept guidance from software. To evaluate the potential performance benefits of these designs, we have simulated five SPLASH benchmark programs on a virtual multiprocessor that supports five directory-based caching protocols. When we compared the off-line optimal performance of this design, wherein each cache line was maintained using the protocol that required the least communication, with the performance achieved when using a single protocol for all lines, we found that use of the "optimal" protocol reduced consistency traffic by 10-80%, with a mean improvement of 25-35%. Cache miss rates also dropped by up to 25%. Thus, the combination of programmable (or tunable) hardware and software able to exploit this added flexibility, e.g., via user pragmas or compiler analysis, could dramatically improve the performance of future shared memory multiprocessors.
Type Text
Publisher University of Utah
Subject Programmable multiprocessor cache controllers; Scalable parallel systems; Shared memory
Subject LCSH Parallel processing (Electronic computers)
Language eng
Bibliographic Citation Carter, J. B., Hibler, M., & Kuramkote, R. R. (1994). Evaluating the potential of programmable multiprocessor cache controllers. 1-24. UUCS-94-040.
Series University of Utah Computer Science Technical Report
Relation is Part of ARPANET
Rights Management ©University of Utah
Format Medium application/pdf
Format Extent 6,110,651 bytes
Identifier ir-main,16196
ARK ark:/87278/s65h8099
Setname ir_uspace
Date Created 2012-06-13
Date Modified 2015-04-23
ID 702276
Reference URL https://collections.lib.utah.edu/ark:/87278/s65h8099
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