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101 A generic operational memory model specification framework for multithreaded program verificationGiven the complicated nature of modern architectural and language level memory model designs, it is vital to have a systematic ap- proach for specifying memory consistency requirements that can support verification and promote understanding. In this paper, we develop a spec- ification methodolog...Multithreaded program verification2003
102 A graphical environment and applications for discrete event and hybrid systems in robotics and automationIn this paper we present an overview for the development of a graphical environment for simulating, analyzing, synthesizing, monitoring, and controlling complex discrete event and hybrid systems within the robotics, automation, and intelligent system domain. We start by presenting an overview of di...Intelligent system domain; Graphical environment1994
103 A shared memory algorithm and proof for the alternative construct in CSPCommunicating Sequential Processes (CSP) is a paradigm for communication and synchronization among distributed processes. The alternative construct is a key feature of CSP that allows nondeterministic selection of one among several possible communicants. Previous algorithms for this construct assume...Shared memory algorithm; Communicating Sequential Processes; CSP1987
104 A tour of the wormOn the evening of November 2, 1988, a self-replicating program was released upon the Internet 1. This program (a worm) invaded VAX and Sun-3 computers running versions of Berkeley UNIX, and used their sources to attack still more computers2. Within the space of hours this program had spread aacross ...Computer worm1989
105 Application specific asynchronous microengines for efficient high-level controlDespite the growing interest in asynchronous circuits programmable asynchronous controllers based on the idea of microprogramming have not been actively pursued Since programmable control is widely used in many commercial ASICs to allow late correction of design errors to easily upgrade product f...Asynchronous microengines1997
106 Application specific asynchronous microgengines for efficient high-level controlDespite the growing interest in asynchronous circuits, programmable asynchronous controllers based on the idea of microprogramming have not been actively pursued. Since programmable control is widely used in many commercial ASICs to allow late correction of design errors, to easily upgrade product ...Asynchronous microgengines; Programmable asynchronous controllers1997
107 Beyond depth-first strategies: improving tabled logic programs through alternative schedulingTabled evaluation ensures termination for programs with finite models by keeping track of which subgoals have been called. Given several variant subgoals in an evaluation, only the fi rst one encountered will use program-clause resolution; the rest will resolve with the answers generated by the f...Alternate scheduling; SLG-WAM; Tabled logic programs1998
108 Characterization and modeling of PIDX parallel I/O for performance optimizationParallel I/O library performance can vary greatly in re- sponse to user-tunable parameter values such as aggregator count, file count, and aggregation strategy. Unfortunately, manual selection of these values is time consuming and dependent on characteristics of the target machine, the underlying fi...2013-01-01
109 Construction of a human torso model from magnetic resonance images for problems in computational electrocardiographyApplying mathematical models to real situations often requires the use of discrete geometrical models of the solution domain. In some cases destructive measurement of the objects under examination is acceptable, but in biomedical applications the measurements come from imaging techniques such as X-r...Human torso model; MRI1994
110 DI - An object-oriented user interface toolbox for modula-2 applicationsThe DI dialog interface tool library for Modula-2 applications described in this paper facilitates the design and implementation of graphical, object-oriented user interfaces for workstations with a graphical screen, a mouse and a keyboard. Much emphasis is put on the portability of the application...DI dialog interface tool1990
111 Dynamically managing the communication-parallelism trade-off in future clustered processorsClustered microarchitectures are an attractive alternative to large monolithic superscalar designs due to their potential for higher clock rates in the face of increasingly wire-delay-constrained process technologies. As increasing transistor counts allow an increase in the number of clusters, th...Clustered architectures; Microarchitecture; Decentralized cache; Interconnects2003
112 Dynamically tunable memory hierarchyThe widespread use of repeaters in long wires creates the possibility of dynamically sizing regular on-chip structures. We present a tunable cache and translation lookaside buffer (TLB) hierarchy that leverages repeater insertion to dynamically trade off size for speed and power consumption on a per...Microarchitecture; High performance microprocessors; Reconfigurable architectures; Energy and performance of on-chip caches; Translation lookaside buffer (TLB); Tunable cache2003-10
113 Evaluating the potential of programmable multiprocessor cache controllersThe next generation of scalable parallel systems (e.g., machines by KSR, Convex, and others) will have shared memory supported in hardware, unlike most current generation machines (e.g., offerings by Intel, nCube, and Thinking Machines). However, current shared memory architectures are constrained b...Programmable multiprocessor cache controllers; Scalable parallel systems; Shared memory1994
114 Graphical man/machine communications: December 1971Semi-Annual Technical Report for period 1 June 1971 to 31 December 1971. This document includes a summary of research activities and facilities at the University of Utah under Contract F30602-70-C-0300. Information conveys important research milestones attained during this period by each of the f...Man/machine communications; Computing systems; Digital waveform processing1971-12
115 High-rate uncorrelated bit extraction for shared secret key generation from channel measurementsSecret keys can be generated and shared between two wireless nodes by measuring and encoding radio channel characteristics without ever revealing the secret key to an eavesdropper at a third location. This paper addresses bit extraction, i.e., the extraction of secret key bits from noisy radio chan...Wireless networks; Multipath fading; Physical layer; Key generation; Secret keys; Bit extraction2010-01
116 Integrating adaptive on-chip storage structures for reduced dynamic powerEnergy efficiency in microarchitectures has become a necessity. Significant dynamic energy savings can be realized for adaptive storage structures such as caches, issue queues, and register files by disabling unnecessary storage resources. Prior studies have analyzed individual structures and their...Microarchitecture2002
117 Investigating applications portability with the Uintah DAG-based runtime system on PetaScale supercomputersPresent trends in high performance computing present formidable challenges for applications code using multicore nodes possibly with accelerators and/or co-processors and reduced memory while still attaining scalability. Software frameworks that execute machine-independent applications code using a ...2013-01-01
118 ISIM: The simulator for the impulse adaptable memory systemThis document describes ISIM, the simulator for the Impulse Adaptable Memory System. Impulse adds two new features to a conventional memory system. First, it supports a configurable, extra level of address remapping at the memory controller. Second, it supports prefetching at the memory controller. ...ISIM; Impulse Adaptable Memory System; Memory systems1999
119 ISP: An optimal out-of-core image-set processing streaming architecture for parallel heterogeneous systemsImage population analysis is the class of statistical methods that plays a central role in understanding the development, evolution, and disease of a population. However, these techniques often require excessive computational power and memory that are compounded with a large number of volumetric inp...2012-01-01
120 Khazana: a flexible wide area data storeKhazana is a peer-to-peer data service that supports efficient sharing and aggressive caching of mutable data across the wide area while giving clients significant control over replica divergence. Previous work on wide-area replicated services focussed on at most two of the following three proper...Khazana; Peer-to-peer data service2003-10-13
121 Middleware support for locality-aware wide area replicationCoherent wide-area data caching can improve the scalability and responsiveness of distributed services such as wide-area file access, database and directory services, and content distribution. However, distributed services differ widely in the frequency of read/write sharing, the amount of conten...Wide-area data caching; Distributed services2004-11-18
122 Multiple target tracking with RF sensor networksRF sensor networks are wireless networks that can localize and track people (or targets) without needing them to carry or wear any electronic device. They use the change in the received signal strength (RSS) of the links due to the movements of people to infer their locations. In this paper, we cons...2014-01-01
123 On fast and accurate detection of unauthorized wireless access points using clock skewsWe explore the use of clock skew of a wireless local area network access point (AP) as its fingerprint to detect unauthorized APs quickly and accurately. The main goal behind using clock skews is to overcome one of the major limitations of existing solutions-the inability to effectively detect Mediu...Clock skews; Unauthorized access; Medium access control; MAC; Address spoofing; Wireless networks; Time Synchronization Function; TSF2010-03
124 Scalable, reliable, power-efficient communication for hardware transactional memoryIn a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true for a large-scale distributed memory system where multiple transactions may attempt to commit simultaneously and co-ordin...Hardware; Transactional memory; Communication2008
125 Semiannual technical report transformation of ADA programs into silicon (1 Sept. 1981- 28 Feb. 1982)This report summarizes the first six months work of the research project, "Transformation of Ada Programs into Silicon." Our project has five main objectives: 1. Develop and document elements of a transformation methodology for converting Ada programs, or program constructs, into VLSI systems which ...ADA programs; VLSI1982
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