Publication Type |
Journal Article |
School or College |
College of Engineering |
Department |
Computing, School of |
Creator |
Balasubramonian, Rajeev |
Other Author |
Madan, Niti; Zhao, Li; Muralimanohar, Naveen; Udipi, Aniruddha; Iyer, Ravishankar; Makineni, Srihari; Newell, Donald |
Title |
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy |
Date |
2009-02 |
Description |
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postulate a 3D chip design that stacks SRAM and DRAM upon processing cores and employs OS-based page coloring to minimize horizontal communication of cache data. We then propose a heterogeneous reconfigurable cache design that takes advantage of the high density of DRAM and the superior power/delay characteristics of SRAM to efficiently meet the working set demands of each individual core. Finally, we analyze the communication patterns for such a processor and show that a tree topology is an ideal fit that significantly reduces the power and latency requirements of the on-chip network. The above proposals are synergistic: each proposal is made more compelling because of its combination with the other innovations described in this paper. The proposed reconfigurable cache model improves performance by up to 19% along with 48% savings in network power. |
Type |
Text |
Publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
First Page |
262 |
Last Page |
274 |
DOI |
10.1109/HPCA.2009.4798261 |
Subject |
Multi-core processors; Cache and memory hierarchy; Non-uniform cache architecture (NUCA); Page coloring; On-chip networks; SRAM/DRAM cache reconfiguration |
Subject LCSH |
Cache memory; Computer storage devices; Computer architecture; Microprocessors; Memory hierarchy (Computer science) |
Language |
eng |
Conference Title |
2009 IEEE 15th International Symposium on High Performance Computer Architecture (HPCA); ; Raleigh, NC, USA |
Bibliographic Citation |
Madan, N., Zhao, L., Muralimanohar, N., Udipi, A., Balasubramonian, R., Iyer, R., Makineni, S., & Newell, D. (2009). Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy. Proceedings - International Symposium on High-Performance Computer Architecture, 4798261, 262-73. |
Rights Management |
(c) 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. http://dx.doi.org/10.1109/HPCA.2009.4798261 |
Format Medium |
application/pdf |
Format Extent |
542,187 bytes |
Identifier |
ir-main,11468 |
ARK |
ark:/87278/s64t72jp |
Setname |
ir_uspace |
ID |
703368 |
Reference URL |
https://collections.lib.utah.edu/ark:/87278/s64t72jp |