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Creator | Title | Description | Subject | Date |
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Khan, Faisal Habib | Challenges and solutions in measuring computer power supply efficiency for 80 PLUS® certification | This paper discusses the techniques, challenges, and results of measuring computer power supply (CPS) efficiency, power factor (PF), and input harmonic currents for the 80 PLUS® program since its beginning in 2002. To date, over 750 power supplies have been tested with many certified for the 80 PL... | | 2009-02 |
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Gondolo, Paolo | Dark matter in the MSSM golden region | Dark matter is examined within the ‘‘golden region'' of the minimal supersymmetric standard model. This region satisfies experimental constraints, including a lower bound on the Higgs mass of 114 GeV, and minimizes fine-tuning of the Z boson mass. Here we impose additional constraints (particula... | MSSM golden region; Neutralinos; Higgs mass | 2009-02 |
3 |
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Balasubramonian, Rajeev | Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches | In future multi-cores, large amounts of delay and power will be spent accessing data in large L2/L3 caches. It has been recently shown that OS-based page coloring allows a non-uniform cache architecture (NUCA) to provide low latencies and not be hindered by complex data search mechanisms. In this ... | Page coloring; Shadow-memory addresses; Cache capacity allocation; Data/page migration; Last level caches; Non-uniform cache architectures (NUCA) | 2009-02 |
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Boehme, Christoph | Influence of disorder on electrically and optically detected electron spin nutation | A numerical study of the influence of disorder in semiconductors on spin-Rabi nutation observed with pulsed electrically or optically detected magnetic-resonance techniques (pEDMR and pODMR, respectively ) is presented. It is shown that transient nutation signals of disordered spin ensembles differ ... | Electron spin nutations | 2009-02 |
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Balasubramonian, Rajeev | Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy | Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postulate a 3D chip design that stacks SRAM and DRAM upon processing cores and employs OS-based page coloring to minimize hori... | Multi-core processors; Cache and memory hierarchy; Non-uniform cache architecture (NUCA); Page coloring; On-chip networks; SRAM/DRAM cache reconfiguration | 2009-02 |