Synthesis of asynchronous control circuits with automatically generated relative timing assumptions

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Publication Type journal article
School or College College of Engineering
Department Electrical & Computer Engineering
Creator Stevens, Kenneth
Other Author Cortadella, Jordi; Kishinevsky, Michael; Burns, Steven M.
Title Synthesis of asynchronous control circuits with automatically generated relative timing assumptions
Date 1999
Description This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ensure functionality. Relative timing assumptions in the form "event a occurs before event b" can be used to remove redundant handshakes and associated logic. This paper presents a method for automatic generation of relative timing assumptions from the untimed specification. These assumptions can be used for area and & lay optimization of the circuit. A set of relative timing constraints sufficient for the correct operation .of the circuit is back-annotated to the designer. Experimental results for control circuits of a prototype iA52 instruction length decoding and steering unit called RAPPID ("Revolving Asynchronous Pentium@Processor Instruction Decoder') shows significant improvements in area and delay over speed-independent circuits.
Type Text
Publisher Institute of Electrical and Electronics Engineers (IEEE)
First Page 324
Last Page 331
Language eng
Bibliographic Citation Cortadella, J., Kishinevsky, M., Burns, S. M., & Stevens, K. S. (1999). Synthesis of asynchronous control circuits with automatically generated relative timing assumptions. Proceedings of the International Conference on Computer-Aided Design (ICCAD-99), 324-31. November.
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Format Extent 1,037,248 bytes
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Reference URL https://collections.lib.utah.edu/ark:/87278/s6vx10rt