Publication Type |
Journal Article |
School or College |
College of Engineering |
Department |
Computing, School of |
Creator |
Balasubramonian, Rajeev |
Other Author |
Semeraro, Greg; Magklis, Grigorios; Albonesi, David H.; Dwarkadas, Sandhya; Scott, Michael L. |
Title |
Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling |
Date |
2002 |
Description |
As clock frequency increases and feature size decreases, clock distribution and wire delays present a growing challenge to the designers of singly-clocked, globally synchronous systems. We describe an alternative approach, which we call a Multiple Clock Domain (MCD) processor in which the chip is divided into several (coarse-grained) clock domains, within which independent voltage and frequency scaling can be performed. Boundaries between domains are chosen to exploit existing queues, thereby minimizing inter-domain synchronization costs. We propose four clock domains, corresponding to the front end (including LI instruction cache), integer units, floating point units, and load-store units (including Ll data cache and L2 cache). We evaluate this design using a simulation infrastructure based on SimpleScalar and Wattch. In an attempt to quantify potential energy savings independent of any particular on-line control strategy, we use of-line analysis of traces from a single-speed run of each of our benchmark applications to identify profitable reconfiguration points for a subsequent dynamic scaling run. Dynamic runs incorporate a detailed model of inter-domain synchronization delays, with latencies for intra-domain scaling similar to the whole-chip scaling latencies of Intel XScale and Transmeta LongRun technologies. Using applications from the MediaBench, Olden, and SPEC2000 benchmark suites, we obtain an average energy-delay product improvement of 20% with MCD compared to a modest 3% savings from voltage scaling a single clock and voltage system. |
Type |
Text |
Publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
First Page |
29 |
Last Page |
40 |
Subject |
Multiple clock domains; Synchronization; Microarchitecture |
Subject LCSH |
Microprocessors; Computer architecture; Microprocessors -- Energy consumption |
Language |
eng |
Bibliographic Citation |
Semeraro, G., Magklis, G., Balasubramonian, R., Albonesi, D. H., Dwarkadas, S., & Scott, M. L. (2002). Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling. 8th International Symposium on High-Performance Computer Architecture (HPCA-8), Cambridge, February 2002, 29-40. |
Rights Management |
(c) 2002 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
Format Medium |
application/pdf |
Format Extent |
1,733,034 bytes |
Identifier |
ir-main,11505 |
ARK |
ark:/87278/s6rn3s3w |
Setname |
ir_uspace |
ID |
703750 |
Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6rn3s3w |