Publication Type |
Journal Article |
School or College |
College of Engineering |
Department |
Computing, School of |
Creator |
Brunvand, Erik L. |
Other Author |
Yang, Jung-Lin |
Title |
Self-timed design with dynamic domino circuits |
Date |
2003 |
Description |
We introduce a simple hierarchical design technique for building high-performance self-timed components using dynamic domino-style circuits. This technique is useful for building handshaking style functional blocks and for self-timed data path components. We wrap the dynamic domino circuit in a wrapper that communicates using a request/acknowledge protocol and mediates the precharge/ evaluate cycle of the dynamic logic. We apply standard bundled delay matching for completion detection but add an early completion feature that can signal completion if function validity can be determined from the output value. The circuit overhead required for this early-acknowledge feature is relatively small, but can provide measurable speedup in some situations. We call this approach semi-bundled delay (SBD). |
Type |
Text |
Publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
First Page |
217 |
Last Page |
219 |
Language |
eng |
Bibliographic Citation |
Yang, J.-L., & Brunvand, E. L. (2003). Self-timed design with dynamic domino circuits. IEEE Annual Symposium on VLSI Design, 217-9. February. |
Rights Management |
(c) 2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
Format Medium |
application/pdf |
Format Extent |
247,017 bytes |
Identifier |
ir-main,15736 |
ARK |
ark:/87278/s6qz2v7x |
Setname |
ir_uspace |
ID |
703699 |
Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6qz2v7x |