| Publication Type |
Journal Article |
| School or College |
College of Engineering |
| Department |
Electrical & Computer Engineering |
| Creator |
Stevens, Kenneth |
| Other Author |
Ginosar, Ran; Rotem, Shai |
| Title |
Relative timing |
| Date |
2003 |
| Description |
Abstract-Relative timing (RT) is introduced as a method for asynchronous design. Timing requirements of a circuit are made explicit using relative timing. Timing can be directly added, removed, and optimized using this style. RT synthesis and verification are demonstrated on three example circuits, facilitating transformations from speed-independent circuits to burst-mode and pulse-mode circuits. Relative timing enables improved performance, area, power, and functional testability of up to a factor of 3x in all three cases. This method is the foundation of optimized timed circuit designs used in an industrial test chip, and may be formalized and automated. |
| Type |
Text |
| Publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
| Volume |
11 |
| Issue |
1 |
| First Page |
129 |
| Last Page |
140 |
| Language |
eng |
| Bibliographic Citation |
Stevens, K., Ginosar, R., & Rotem, S. (2003). Relative timing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11(1), 129-40. Feb. |
| Rights Management |
(c) 2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
| Format Medium |
application/pdf |
| Format Extent |
575,746 bytes |
| Identifier |
ir-main,15288 |
| ARK |
ark:/87278/s6m33ddm |
| Setname |
ir_uspace |
| ID |
707374 |
| Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6m33ddm |
