Publication Type |
Journal Article |
School or College |
College of Engineering |
Department |
Electrical & Computer Engineering |
Creator |
Stevens, Kenneth |
Other Author |
Gebhardt, Daniel |
Title |
Power reduction through physical placement of asynchronous routers |
Date |
2009 |
Description |
Our work reduces power consumption by minimizing wirelength and hop-count of an asynchronous NoC using simulated annealing and force-directed algorithms. Asynchronous NoCs (aNoCs) can provide important benefits over clocked NoCs. However, there is little published research on generating a custom, optimized aNoC for a fixedfunction, power-constrained system-on-chip (SoC). Such tools must consider physical SoC properties and especially NoC link delay and power. Our research is motivated by this need, and the mantra that ?transistors are fast, wires are slow and power-hungry,? due to process scaling differences between transistors and global wires. |
Type |
Text |
Publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
Language |
eng |
Bibliographic Citation |
Daniel G., & Stevens, K. S. (2009). Power reduction through physical placement of asynchronous routers. 3rd IEEE International Symposium on Network-on-Chip, 92. May. |
Rights Management |
© 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
Format Medium |
application/pdf |
Format Extent |
81,710 bytes |
Identifier |
ir-main,15275 |
ARK |
ark:/87278/s6h71090 |
Setname |
ir_uspace |
ID |
705656 |
Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6h71090 |