Publication Type |
Journal Article |
School or College |
College of Engineering |
Department |
Computing, School of |
Creator |
Balasubramonian, Rajeev |
Other Author |
Dwarkadas, Sandhya; Albonesi, David H. |
Title |
Reducing the complexity of the register file in dynamic superscalar processors |
Date |
2001 |
Description |
Dynamic superscalar processors execute multiple instructions out-of-order by looking for independent operations within a large window. The number of physical registers within the processor has a direct impact on the size of this window as most in-flight instructions require a new physical register at dispatch. A large multi-ported register file helps improve the instruction-level parallelism (ILP), but may have a detrimental effect on clock speed, especially in future wire-limited technologies. In this paper, we propose a register file organization that reduces register file size and port requirements for a given amount of ILP. We use a two-level register file organization to reduce register file size requirements, and a banked organization to reduce port requirements. We demonstrate empirically that the resulting register file organizations have reduced latency and (in the case of the banked organization) energy requirements for similar instructions per cycle (IPC) performance and improved instructions per second (IPS) performance in comparison to a conventional monolithic register file. The choice of organization is dependent on design goals. |
Type |
Text |
Publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
First Page |
237 |
Last Page |
248 |
DOI |
10.1109/MICRO.2001.991122 |
Subject |
Dynamic superscalar processors; Register file; Instruction-level parallelism; Microarchitecture; Reorder buffer |
Subject LCSH |
Microprocessors; Computer architecture; Buffer storage (Computer science) |
Language |
eng |
Conference Title |
34th ACM/IEEE International Symposium on Microarchitecture; 1-5 Dec. 2001; Austin, TX, USA |
Bibliographic Citation |
Balasubramonian, R., Dwarkadas, S., & Albonesi, D. H. (2001). Reducing the complexity of the register file in dynamic superscalar processors. 34th International Symposium on Microarchitecture (MICRO-34), Austin, December 2001, 237-48. |
Rights Management |
(c) 2001 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. http://dx.doi.org/10.1109/MICRO.2001.991122 |
Format Medium |
application/pdf |
Format Extent |
1,199,635 bytes |
Identifier |
ir-main,11506 |
ARK |
ark:/87278/s6g16j1j |
Setname |
ir_uspace |
ID |
703585 |
Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6g16j1j |