CMOS analog map decoder for (8,4) hamming code

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Publication Type Journal Article
School or College College of Engineering
Department Electrical & Computer Engineering
Creator Myers, Chris J.
Other Author Winstead, Chris; Dai, Jie; Yu, Shuhuan; Harrison, Reid R.; Schlegel, Christian
Title CMOS analog map decoder for (8,4) hamming code
Date 2004
Description Abstract-Design and test results for a fully integrated translinear tail-biting MAP error-control decoder are presented. Decoder designs have been reported for various applications which make use of analog computation, mostly for Viterbi-style decoders. MAP decoders are more complex, and are necessary components of powerful iterative decoding systems such as Turbo codes. Analog circuits may require less area and power than digital implementations in high-speed iterative applications. Our (8, 4) Hamming decoder, implemented in an AMI 0.5- m process, is the first functioning CMOS analog MAP decoder. While designed to operate in subthreshold, the decoder also functions above threshold with a small performance penalty. The chip has been tested at bit rates up to 2 Mb/s, and simulations indicate a top speed of about 10 Mb/s in strong inversion. The decoder circuit size is 0.82 mm2, and typical power consumption is 1 mW at 1 Mb/s.
Type Text
Publisher Institute of Electrical and Electronics Engineers (IEEE)
Volume 39
Issue 1
First Page 122
Last Page 131
Language eng
Bibliographic Citation Winstead, C., Dai, J., Yu, S., Myers, C., Harrison, R. R., & Schlegel, C. (2004). CMOS analog map decoder for (8,4) hamming code. Journal of Solid State Circuits, 39(1), 122-31. January.
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Format Medium application/pdf
Format Extent 429,948 bytes
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Reference URL https://collections.lib.utah.edu/ark:/87278/s6fn1qks