Publication Type |
Journal Article |
School or College |
College of Engineering |
Department |
Electrical & Computer Engineering |
Creator |
Myers, Chris J. |
Other Author |
Belluomini, Wendy J. |
Title |
Timed state space exploration using POSETs |
Date |
2000 |
Description |
Abstract-This paper presents a new timing analysis algorithm for efficient state space exploration during the synthesis of timed circuits or the verification of timed systems. The source of the computational complexity in the synthesis or verification of a timed system is in finding the reachable timed state space. We introduce a new algorithm which utilizes geometric regions to represent the timed state space and partially ordered sets (POSET's) to minimize the number of regions necessary. This algorithm operates on specifications sufficiently general to describe practical circuits, as well as other timed systems. The algorithm is applied to several examples showing significant improvement in runtime and memory usage. |
Type |
Text |
Publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
Volume |
19 |
Issue |
5 |
First Page |
501 |
Last Page |
520 |
Language |
eng |
Bibliographic Citation |
Belluomini, W. J., & Myers, C. J. (2000). Timed state space exploration using POSETs. IEEE Transactions on CAD, 19(5), 501-20. May. |
Rights Management |
(c) 2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
Format Medium |
application/pdf |
Format Extent |
494,905 bytes |
Identifier |
ir-main,14989 |
ARK |
ark:/87278/s6f486gq |
Setname |
ir_uspace |
ID |
704354 |
Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6f486gq |