Publication Type |
Journal Article |
School or College |
College of Engineering |
Department |
Computing, School of |
Creator |
Balasubramonian, Rajeev |
Other Author |
Muralimanohar, Naveen; Ramani, Karthik; Venkatachalapathy, Venkatanand |
Title |
Microarchitectural wire management for performance and power in partitioned architectures |
Date |
2005 |
Description |
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low power. In such architectures, inter-partition communication over global wires has a significant impact on overall processor performance and power consumption. VLSI techniques allow a variety of wire implementations, but these wire properties have previously never been exposed to the microarchitecture. This paper advocates global wire management at the microarchitecture level and proposes a heterogeneous interconnect that is comprised of wires with varying latency, bandwidth, and energy characteristics. We propose and evaluate microarchitectural techniques that can exploit such a heterogeneous interconnect to improve performance and reduce energy consumption. These techniques include a novel cache pipeline design, the identification of narrow bit-width operands, the classification of non-critical data, and the detection of interconnect load imbalance. For a dynamically scheduled partitioned architecture, our results demonstrate that the proposed innovations result in up to 11% reductions in overall processor ED2, compared to a baseline processor that employs a homogeneous interconnect. |
Type |
Text |
Publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
First Page |
28 |
Last Page |
39 |
DOI |
10.1109/HPCA.2005.21 |
Subject |
Microarchitecture; Partitioned architectures; Heterogeneous interconnects; Cache access |
Subject LCSH |
Computer architecture; Microprogramming; Microprocessors; Electric wiring; Cache memory; Microprocessors -- Energy consumption |
Language |
eng |
Conference Title |
11th International Symposium on High-Performance Computer Architecture; 12-16 Feb. 2005; San Francisco, CA, USA |
Bibliographic Citation |
Balasubramonian, R., Muralimanohar, N., Ramani, K., & Venkatachalapathy, V. (2005). Microarchitectural wire management for performance and power in partitioned architectures. Proceedings - International Symposium on High-Performance Computer Architecture, 28-39. |
Rights Management |
(c) 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. http://dx.doi.org/10.1109/HPCA.2005.21 |
Format Medium |
application/pdf |
Format Extent |
211,603 bytes |
Identifier |
ir-main,11479 |
ARK |
ark:/87278/s6dv230v |
Setname |
ir_uspace |
ID |
702684 |
Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6dv230v |