Architecting efficient interconnects for large caches with CACTI 6.0

Efficiently executing multithreaded applications on future multicores will require fast intercore communication. Most of this communication happens via reads and writes to large shared caches in the memory hierarchy. Microprocessor performance and power will be strongly influenced by the long interconnects that must be traversed to access a cache bank. The coming decade will likely see many innovations to the multicore cache hierarchy: policies for data placement and migration, logical and physical cache reconfiguration, optimizations to the on-chip network fabric, and so on.