A single chip low power asynchronous implementation of an FFT algorithm for space applications

Update Item Information
Publication Type Journal Article
School or College College of Engineering
Department Electrical & Computer Engineering
Creator Stevens, Kenneth
Other Author Hunt, B. W.; Suter, B. W.; Gelosh, D. S.
Title A single chip low power asynchronous implementation of an FFT algorithm for space applications
Date 1998
Description A fully asynchronous _x000C_fixed point FFT processor is introduced for low power space applications. The architecture is based on an algorithm developed by Suter and Stevens specifi_x000C_cally for a low power implementation. The novelty of this architecture lies in its high localization of components and pipelining with no need to share a global memory. High throughput is attained using large numbers of small, local components working in parallel. A derivation of the algorithm from the discrete Fourier transform is presented followed by a discussion of circuit design parameters specifi_x000C_cally those relevant to space applications. A survey of this application specifi_x000C_c architecture is included with a detailed look at the design of the complex-valued Booth multiplier to demonstrate the design methodology of this project. Finally, simulation results based on layout extractions are presented and an outline for future work is given.
Type Text
Publisher Institute of Electrical and Electronics Engineers (IEEE)
First Page 216
Last Page 223
Language eng
Bibliographic Citation Hunt, B. W., Steven, K. S., Suter, B. W., & Gelosh, D. S. (1998). A single chip low power asynchronous implementation of an FFT algorithm for space applications. Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC-98), 216-23. April.
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Format Medium application/pdf
Format Extent 200,830 bytes
Identifier ir-main,15308
ARK ark:/87278/s6b85smv
Setname ir_uspace
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Reference URL https://collections.lib.utah.edu/ark:/87278/s6b85smv