| Publication Type |
technical report |
| School or College |
College of Engineering |
| Department |
Computing, School of |
| Creator |
Yoo, Jae-tack |
| Title |
High-speed conterflow-clocked pipelining illustrated on the design of subband vector quantizatizer chips |
| Date |
1995-12 |
| Description |
This dissertation introduces Counterflow-Clocked (C2) pipelining and discusses its usefulness and limitations to build large, high speed VLSI chips. It also presents the design of an image compression chip set to implement subband vector quantization that can handle HDTV data rates with reasonable VLSI chip sizes. |
| Type |
Text |
| Publisher |
University of Utah |
| Subject |
VLSI chips; counterflow-clocked pipelining; computers |
| Subject LCSH |
Image compression--Research; Computers--Circuits; Integrated circuits--Very large scale integration. |
| Language |
eng |
| Bibliographic Citation |
Yoo, J. (1995). High-speed conterflow-clocked pipelining illustrated on the design of subband vector quantizatizer chips |
| Series |
University of Utah Computer Science Technical Report |
| Relation is Part of |
ARPANET |
| Format Medium |
application/pdf |
| Format Extent |
1,227,517 Bytes |
| File Name |
Yoo-High_Speed_Counterflow_Clock.pdf |
| Conversion Specifications |
Original scanned with Kirtas 2400 and saved as 400 ppi uncompressed TIFF. PDF generated by Adobe Acrobat Pro X for CONTENTdm display |
| ARK |
ark:/87278/s68k996p |
| Setname |
ir_computersa |
| ID |
95223 |
| Reference URL |
https://collections.lib.utah.edu/ark:/87278/s68k996p |
