Publication Type |
technical report |
School or College |
College of Engineering |
Department |
Computing, School of |
Creator |
Gopalakrishnan, Ganesh |
Other Author |
Fujimoto, Richard M.; Akella Venkatesh; Mani, Narayana S. |
Title |
HOP: a process model for synchronous hardware semantics, and experiments in process composition |
Date |
1988 |
Description |
We present a language "Hardware viewed as Objects and Processes" (HOP) for specifying the structure, behavior, and timing of hardware systems. HOP embodies a simple process model for lock-step synchronous processes. An absproc specification written in HOP describes the externally observable behavior of a process. A collection of absprocs may be composed to form a larger process, using the operators parallel composition, renaming, and hiding. In this paper we present the communication primitives of HOP, illustrate HOP through several examples, and then present its operational semantics. Then we present the role played by HOP in in three VLSI design activities: (i) inferring concise behavioral descriptions of systems from their structural descriptions; (ii) static detection of control timing errors during behavioral inferrence; (Hi) productive and runtime efficient functional simulation using the inferred behavior. |
Type |
Text |
Publisher |
University of Utah |
First Page |
1 |
Last Page |
43 |
Subject |
HOP; Synchronous hardware semantics |
Language |
eng |
Bibliographic Citation |
Gopalakrishnan, G., Fujimoto, R. M., Akella V., & Mani, N. S. (1988). HOP: a process model for synchronous hardware semantics, and experiments in process composition. 1-43. UUCS-88-012. |
Series |
University of Utah Computer Science Technical Report |
Relation is Part of |
ARPANET |
Rights Management |
©University of Utah |
Format Medium |
application/pdf |
Format Extent |
18,707,124 bytes |
Identifier |
ir-main,16150 |
ARK |
ark:/87278/s68d0dc1 |
Setname |
ir_uspace |
ID |
702839 |
Reference URL |
https://collections.lib.utah.edu/ark:/87278/s68d0dc1 |