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CreatorTitleDescriptionSubjectDate
151 Brunvand, Erik L.Reduced latency self-timed FIFO circuitsSelf-timed flow-through FIFOs are constructed easily using only a single C-element as control for each stage of the FIFO. Throughput can be very high in FIFOs of this type because new data can be sent to the FIFO after communicating locally with only the first element of the FIFO. Therefore the thro...FIFO circuits; Self-timed; Flow-through; Reduced latency1994
152 Brunvand, Erik L.ACT: A DFT tool for self-timed circuitsThis paper presents a Design for Testability (DFT) tool called ACT (Asynchronous Circuit Testing) which uses a partial scan technique to make macro-module based selftimed circuits testable. The ACT tool is the first oFits kind for testing macro-module based self-timed circuits. ACT modifies design...1997
153 Brunvand, Erik L.Practical advances in asynchronous design and in asynchronous/synchronous interfacesAsynchronous systems are being viewed as an increasingly viable alternative to purely synchronous systems. This paper gives an overview of the current state of the art in practical asynchronous circuit and system design in four areas: controllers, datapaths, processors, and the design of asynchr...1999
154 Dawson, KyleTechnology development for 4k x 4k, back-illuminated, fully depleted scientific CCD imagersWe have developed scientific charge-coupled devices (CCDs) that are fabricated on high-resistivity, n-type silicon substrates, and have demonstrated fully depleted operation for substrate thicknesses of 200-675 μm with formats as large as 2048 × 4096 (15 μm pixels) and 3512 × 3512 (10.5 μm pix...Gettering2007-10
155 Myers, Chris J.; Gopalakrishnan, GaneshAchieving fast and exact hazard-free logic minimization of extended burst-mode gC finite state machinesAbstract This paper presents a new approach to two-level hazard-free logic minimization in the context of extended burst-mode finite state machine synthesis targeting generalized C-elements (gC). No currently available minimizers for literal-exact two-level hazard-free logic minimization of extende...2000
156 Williams, Clayton C.Advances in experimental technique for quantitative two dimensional dopant profiling by scanning capacitance microscopySeveral advances have been made toward the achievement of quantitative two-dimensional dopant and carrier profiling. To improve the dielectric and charge properties of the oxide-silicon interface, a method of low temperature heat treatment has been developed which produces an insulating layer with c...Doping; Scanning capacitance microscope; SCM1999
157 Myers, Chris J.Verification of timed circuits with failure directed abstractionsThis paper presents a method to address state explosion in timed circuit verification by using abstraction directed by the failure model. This method allows us to decompose the verification problem into a set of subproblems, each of which proves that a specific failure condition does not occur. To...2003
158 Harrison, Reid R.; Myers, Chris J.; Schlegel, ChristianCell library for automatic synthesis of analog error control decodersThis paper presents a cell library for automatic synthesis of analog error control decoders. By using some basic cells, analog ermr control decoders can be automatically synthesized. Also, using automatic synthesis based on this cell library, the circuit performance is not degraded and the circuit i...2002
159 Harrison, Reid R.Low-power, low-noise CMOS amplifier for neural recording applicationsThere is a need among scientists and clinicians for lownoise, low-power biosignal amplifiers capable of amplifying signals in the mHz to kHz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully-implantable multielectrode arrays has created the nee...2002-01-01
160 Harrison, Reid R.Wireless integrated circuit for the acquisition of electrocorticogram signalsAbstract-We present the design and characterization of amplifiers and control logic for an integrated circuit designed to record electrocorticograms (ECoG) from the surface of the brain. The chip, which was fabricated in a 0.6-μm BiCMOS process, contains 100 amplifiers, control logic, and circuits...2010
161 Gopalakrishnan, GaneshCase studies in symbolic model checkingThe need to formally verify hardware and software systems before they are deployed the real world has been recognized for several decades now. This is especially true of concurrent systems that are even more difficult to debug than sequential systems. For example, many of the protocols that get emp...Symbolic model checking; Hardware verification; Software verification1994
162 Brunvand, Erik L.Practical advances in asynchronous designRecent practical advances in asynchronous circuit and system design have resulted in renewed interest by circuit designers. Asynchronous systems are being viewed as in increasingly viable alternative to globally synchronous system organization. This tutorial will present the current state of the art...1997
163 Harrison, Reid R.Micropower circuits for bidirectional wireless telemetry in neural recording applicationsState-of-the art neural recording systems require electronics allowing for transcutaneous, bidirectional data transfer. As these circuits will be implanted near the brain, they must be small and low power. We have developed micropower integrated circuits for recovering clock and data signals over ...Micropower circuits; Neural recording systems; Low-power CMOS circuits, RF telemetry; Transcutaneous data link; Transmitter2005-01-01
164 Williams, Clayton C.Direct imaging of SiO2 thickness variation on Si using modified atomic force microscopeFabrication techniques of metal-oxide-semiconductor ~(MOS) transistors have been improved very rapidly during the last several decades. With this trend, scaling down of MOS transistors is necessary to improve the speed of circuits and the packing density of discrete devices. Both lateral and vertic...Silicon dioxide; Oxide layer; Phosphorus ions; Oxide capacitance; Dopant profile1996-03-01
165 Gopalakrishnan, GaneshSome recent asynchronous system design methodologiesWe present an in-depth study of some techniques for asynchronous system design, analysis, and verification. After defining basic terminology, we take one simple example - a four-phase t o two-phase converter - and present its design using (a) classical flow-tables; (b) Signal Transition Graphs of [...Asynchronous system design1990
166 Gopalakrishnan, GaneshEfficient symbolic simulation based verification using the parametric form of boolean expressions (rev.)We present several new techniques to make symbolic simulation based verification efficient. These techniques hinge on the use of the parametric form of a boolean expression (e.g. the parametric form for the boolean expression XQ V -<xi is the equivalent expression 3a b . (XQ = a V 6) A (xi = b), whe...Symbolic simulation; Verification1991
167 Stevens, KennethAn A-FPGA architecture for relative timing based asynchronous designsThis paper presents an asynchronous FPGA architecture that is capable of implementing relative timing based asynchronous designs. The architecture uses the Xilinx 7-Series architecture as a starting point and proposes modifications that would make it asynchronous design capable while keeping it full...2014-01-01
168 Khan, Faisal HabibMultiple load-source integration in a multilevel modular capacitor clamped DC-DC converter featuring fault tolerant capabilityAbstract-A multilevel modular capacitor clamped dc-dc converter (MMCCC) will be presented in this paper with some of its advantageous features. By virtue of the modular nature of the converter, it is possible to integrate multiple loads and sources to the converter at the same time. The modular con...2007
169 Khan, Faisal HabibUniversal multilevel DC-DC converter with variable conversion ratio, high compactness factor and limited isolation featureA multilevel dc-dc converter with programmable conversion ratio (CR) is presented in this paper. This converter is a modified version of the MMCCC converter. A universal version of the MMCCC is developed in this paper, and the CR can be easily changed within a wide range. The MMCCC converter is bas...2008-02
170 Brunvand, Erik L.Editorial asynchronous architectureAsynchronous design is enjoying a worldwide resurgence of interest following several decades in obscurity. Many of the early computers employed asynchronous design techniques, but since the mid 1970s almost all digital design has been based around the use of a central clock. The clock simplifies mos...1996-01-01
171 Gopalakrishnan, GaneshA compositional model for synchronous VLSI systemsCurrently available hardware specification languages have two serious deficiencies: (i) inadequate protocol definition capabilities; (ii) lack of a compositional model. We now explain these in more detail.Very large scale integration; VLSI systems1987
172 Brunvand, Erik L.Performance analysis and optimization of asynchronous circuitsAsynchronous/Self-timed circuits are beginning to attract renewed attention as promising means of dealing with the complexity of modern VZSI designs. Very few analysis techniques or tools are available for estimating their performance. In this paper we adapt the theory of Generalized Timed Petri-n...1994
173 Lupton, John MarkStimulated emission depletion of triplet excitons in a phosphorescent organic laserTriplet formation is investigated in an optically pumped polymer laser by detecting the phosphorescence emission after excitation. A clear correlation is observed between the onset of lasing and a saturation of phosphorescence intensity due to stimulated emission depletion of the singlet state and t...Triplet excitons; Triplet formation; Emission depletion; Phosphorescent organic laser; Optically pumped polymer laser2006
174 Richardson, William F.; Brunvand, Erik L.The NSR processor prototypeThe NSR Non Synchronous RISC processor is a general purpose processor structured as a collection of self timed units that operate concurrently and communicate over bundled data channels in the style of micropipelines?? These units correspond to standard synchronous pipeline stages such as Instr...Self-timed Systems; Asynchronous systems; Micropipelines; FPGAs; RISC processor1992
175 Gopalakrishnan, GaneshPeephole optimization of asynchronous networks through process composition and burst-mode machine generationIn this paper we discuss the problem of improving the e ciency of macromodule networks generated through asynchronous high level synthesis We compose the behaviors of the modules in the sub network being optimized using Dill s trace theoretic operators to get a single behavioral description for ...Macromodule networks; Peephole; Asynchronous networks1993
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