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126 Regehr, JohnMemory safety and untrusted extensions for TinyOSSensor network applications should be reliable. However, TinyOS, the dominant sensor net OS, lacks basic building blocks for reliable software systems: memory protection, isolation, and safe termination. These features are typically found in general-purpose operating systems but are believed to be t...2006-01-01
127 Regehr, JohnLock inference for systems softwareWe have developed task scheduler logic (TSL) to automate reasoning about scheduling and concurrency in systems software. TSL can detect race conditions and other errors as well as supporting lock inference: the derivation of an appropriate lock implementation for each critical section in a system. L...2003-01-01
128 Regehr, JohnInterface contracts for TinyOSTinyOS applications are built with software components that communicate through narrow interfaces. Since components enable fine-grained code reuse, this approach has been successful in creating applications that make very efficient use of the limited code and data memory on sensor network nodes. How...2007-01-01
129 Regehr, JohnHow to rapidly prototype a real-time schedulerImplementing a new scheduling algorithm in an OS kernel is often an important step in scheduling research because it permits evaluation of the algorithm's performance on real workloads. However, developing a new scheduler is not a trivial task because it requires sophisticated programming skills and...2002-01-01
130 Regehr, JohnFinding and understanding bugs in C compilersCompilers should be correct. To improve the quality of C compilers, we created Csmith, a randomized test-case generation tool, and spent three years using it to find compiler bugs. During this period we reported more than 325 previously unknown bugs to compiler developers. Every compiler we tested w...2011-01-01
131 Hansen, Charles D.FluoRender: An application of 2D image space methods for 3D and 4D confocal microscopy data visualization in neurobiology research2D image space methods are processing methods applied after the volumetric data are projected and rendered into the 2D image space, such as 2D filtering, tone mapping and compositing. In the application domain of volume visualization, most 2D image space methods can be carried out more efficiently t...2012-01-01
132 Silva, Claudio T.ISP: An optimal out-of-core image-set processing streaming architecture for parallel heterogeneous systemsImage population analysis is the class of statistical methods that plays a central role in understanding the development, evolution, and disease of a population. However, these techniques often require excessive computational power and memory that are compounded with a large number of volumetric inp...2012-01-01
133 Regehr, JohnOffline compression for on-chip RAMWe present offline RAM compression, an automated source-to-source transformation that reduces a program's data size. Statically allocated scalars, pointers, structures, and arrays are encoded and packed based on the results of a whole-program analysis in the value set and pointer set domains. We tar...2007-01-01
134 Regehr, JohnPh.D. Proposal: hierarchical loadable schedulersThe processors in workstations, personal computers, and servers are becoming increasingly powerful, enabling them to run new kinds of applications, and to simultaneously run combinations of applications that were previously infeasible. However, fast hardware is not enough-the operating system must e...1999-01-01
135 Regehr, JohnUsing hierarchical scheduling to support soft real-time applications in general-purpose operating systemsThe CPU schedulers in general-purpose operating systems are designed to provide fast response time for interactive applications and high throughput for batch applications. The heuristics used to achieve these goals do not lend themselves to scheduling real-time applications, nor do they meet other s...2001-01-01
136 Regehr, JohnVertically integrated analysis and transformation for embedded softwareProgram analyses and transformations that are more aggressive and more domain-specific than those traditionally performed by compilers are one possible route to achieving the rapid creation of reliable and efficient embedded software. We are creating a new framework for Vertically Integrated Program...2003-01-01
137 Regehr, JohnRandom testing of interrupt-driven softwareInterrupt-driven embedded software is hard to thoroughly test since it usually contains a very large number of executable paths. Developers can test more of these paths using random interrupt testing-firing random interrupt handlers at random times. Unfortunately, na¨ıve application of random test...2005-01-01
138 Regehr, JohnThread verification vs. interrupt verificationInterrupts are superficially similar to threads, but there are subtle semantic differences between the two abstractions. This paper compares and contrasts threads and interrupts from the point of view of verifying the absence of race conditions. We identify a small set of extensions that permit thre...2006-01-01
139 Pascucci, ValerioTopology verification for isosurface extractionThe broad goals of verifiable visualization rely on correct algorithmic implementations. We extend a framework for verification of isosurfacing implementations to check topological properties. Specifically, we use stratified Morse theory and digital topology to design algorithms which verify topolog...2012-01-01
140 Pascucci, ValerioTopological analysis and visualization of cyclical behavior in memory reference tracesWe demonstrate the application of topological analysis techniques to the rather unexpected domain of software visualization. We collect a memory reference trace from a running program, recasting the linear flow of trace records as a high-dimensional point cloud in a metric space. We use topological ...2012-01-01
141 Regehr, JohnTwo case studies in predictable application scheduling using Rialto/NTThis paper analyzes the results of two case studies in applying the Rialto/NT scheduler to real Windows 2000 applications. The first study is of a soft modem-a modem whose signal processing work is performed on the host CPU, rather than on a dedicated signal processing chip. The second is of an audi...2001-01-01
142 Regehr, JohnVolatiles are miscompiled, and what to do about itC's volatile qualifier is intended to provide a reliable link between operations at the source-code level and operations at the memory-system level. We tested thirteen production-quality C compilers and, for each, found situations in which the compiler generated incorrect code for accessing volatile...2008-01-01
143 Cohen, ElaineVolume rendering with multidimensional peak findingPeak finding provides more accurate classification for direct volume rendering by sampling directly at local maxima in a transfer function, allowing for better reproduction of high-frequency features. However, the 1D peak finding technique does not extend to higherdimensional classification. In this...2012-01-01
144 Gopalakrishnan, Ganesh; Humphrey, Alan Parker; Derrick, Christopher GladeAn integration of dynamic MPI formal verification within eclipse PTPOur research goals were to verify practical MPI programs for deadlocks, resource leaks, and assertion violations at the push of a button and be able to easily visualize the results. We also sought to integrate these capabilities with the Eclipse IDE via an Eclipse plug-in for the Parallel Tools Plat...Verification; Graphical User Interfaces; Dynamic Interleaving Reduction; Message Passing; MPI; Multi-core; Eclipse Parallel Tools Platform; Trapeze Interactive Poster2010-03-15
145 Li, Guodong; Gopalakrishnan, Ganesh; Kirby, Robert Michael IiPUG : A Symbolic Verifier of GPU ProgramsPUG is a automated verifier for GPU programs written in C/CUDA. PUG verifies GPU kernels for Data Races, Barrier mismatches, Totally wrong results, and Weak memory model related bugs. SMT-based correctness checking methods for these error are often more scalable, general and modular.2010-10-06
146 Awasthi, Manu; Nellans, David W.; Sudan, Kshitij; Balasubramonian, RajeevABP : predictor based management of DRAM row buffersDRAM accesses are costly, especially in multicore systems. Future CMPs will run a mixed load of workloads/threads. Destructive interference at memory controller, spatio-temporal locality lost! DRAM row-buffer hits are least expensive, row-conflicts are most. Randomized memory access patterns re...2010-10-06
147 Thulasinathan, Aravindan; Pascucci, Valerio; Tierny, JulienTopology Based Surface Meshing and MorphingMorphing is a seamless transition from one image to the other, used in animation and motion pictures. Mesh Parameterization used in this process is a fundamental tool used for domain remeshing. In case of 2-manifolds for example, most approaches require that the input mesh be cut into one or mor...2010-10-06
148 Balasubramonian, RajeevStaged reads: mitigating the impact of DRAM writes on DRAM readsMain memory latencies have always been a concern for system performance. Given that reads are on the criti- cal path for CPU progress, reads must be prioritized over writes. However, writes must be eventually processed and they often delay pending reads. In fact, a single channel in the main memory ...2012-01-01
149 Sudan, KshitijEfficient scrub mechanisms for error-prone emerging memoriesMany memory cell technologies are being considered as possible replacements for DRAM and Flash technologies, both of which are nearing their scaling limits. While these new cells (PCM, STT-RAM, FeRAM, etc.) promise high density, better scaling, and non-volatility, they introduce new challenges. Solu...2012-01-01
150 Johnson, Robert R.Patterns of patternsPurpose of this Poster is to demonstrate that it takes the patterns of values in all the many dimensions to place each patient in the final patterns shown in each of the 5 charts. The final patterns determine the ability of each technology to identify or distinguish patients in each class. It is p...Gene patterns; Colon cancer; Trapeze Interactive poster2010-03-15
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