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Creator | Title | Description | Subject | Date |
101 |
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Riloff, Ellen M. | Recognizing and organizing opinions expressed in the world press | Tomorrow's question answering systems will need to have the ability to process information about beliefs, opinions, and evaluations-the perspective of an agent. Answers to many simple factual questions-even yes/no questions-are affected by the perspective of the information source. For example... | Opinions; Opinion recognition; World press; MPQA project; Multiple perspectives | 2003 |
102 |
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Stevens, Kenneth | A single chip low power asynchronous implementation of an FFT algorithm for space applications | A fully asynchronous _x000C_fixed point FFT processor is introduced for low power space applications. The architecture is based on an algorithm developed by Suter and Stevens specifi_x000C_cally for a low power implementation. The novelty of this architecture lies in its high localization of compo... | | 1998 |
103 |
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Hughes, Kelly T. | ATPase-Independent Type-III Protein Secretion in Salmonella enterica | Type-III protein secretion systems are utilized by gram-negative pathogens to secrete building blocks of the bacterial flagellum, virulence effectors from the cytoplasm into host cells, and structural subunits of the needle complex. The flagellar type-III secretion apparatus utilizes both the energy... | | 2014-01-01 |
104 |
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Myers, Chris J.; Stevens, Kenneth | An asynchronous instruction length decoder | Abstract-This paper describes an investigation of potential advantages and pitfalls of applying an asynchronous design methodology to an advanced microprocessor architecture. A prototype complex instruction set length decoding and steering unit was implemented using self-timed circuits. [The Revolvi... | | 2001 |
105 |
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Stevens, Kenneth; Myers, Chris J. | An asynchronous instruction length decoder | This paper describes an investigation of potential advantages and pitfalls of applying an asynchronous design methodology to an advanced microprocessor architecture. A prototype complex instruction set length decoding and steering unit was implemented using self-timed circuits. [The Revolving Async... | | 2001 |
106 |
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Balasubramonian, Rajeev | Dynamically tuning processor resources with adaptive processing | Using adaptive processing to dynamically tune major microprocessor resources, developers can achieve greater energy efficiency with reasonable hardware and software overhead while avoiding undue performance loss. | Adaptive processing; Energy efficiency; DRI-cache | 2003-12 |
107 |
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Khan, Faisal Habib | Reliability analysis and performance degradation of a boost converter | In general, power converters are operated in closed-loop systems, and any characteristic variations in one component will simultaneously alter the operating point of other components, resulting in a shift in overall reliability profile. This interdependence makes the reliability of a converter a com... | | 2014-01-01 |
108 |
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Miller, Jan D.; Lin, Chen-Luh | On-line washability analysis for the control of coarse coal cleaning circuits | In view of the success of recent laboratory studies using X-ray computed tomography (CT) to determine coal washability and with the availability of high-speed CT systems, it now seems possible to design an on-stream washability system for the control of coarse coal-cleaning circuits. Design features... | On-stream washability; CT analyzer; Coal washability | 1995 |
109 |
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Khan, Faisal Habib | Efficiency characterization and impedance modeling of a multilevel switched-capacitor converter using pulse dropping switching scheme | Apulse dropping switching technique (PDT) has been presented in this paper to accomplish variable conversion ratio (CR) in a multilevel modular capacitor-clamped dc-dc converter in the step-up conversion mode. The switching pattern is generated by comparing a triangular wave with a rectangular wave,... | | 2014-01-01 |
110 |
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Gopalakrishnan, Ganesh | High level optimizations in compiling process descriptions to asynchronous circuits | Asynchronous/'Self-Timed designs are beginning to attract attention as promising means of dealing with the complexity of modern VLSI technology. In this paper, we present our views on why asynchronous systems matter. We then present details of our high level synthesis tool SHILPA that can automatic... | Self-timed; VLSI | 1992 |
111 |
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Myers, Chris J. | Efficient exact two-level hazard-free logic minimization | Abstract This paper presents a new approach to two-level hazard-free sum-of-products logic minimization. No currently available minimizers for single-output literal-exact two-level hazard-free logic minimization can handle large circuits without synthesis times ranging up over thousands of seconds.... | | 2001 |
112 |
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Myers, Chris J. | CMOS analog map decoder for (8,4) hamming code | Abstract-Design and test results for a fully integrated translinear tail-biting MAP error-control decoder are presented. Decoder designs have been reported for various applications which make use of analog computation, mostly for Viterbi-style decoders. MAP decoders are more complex, and are necess... | | 2004 |
113 |
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Bergerson, Amy A. | Gender disparity in engineering: results and analysis from school counselors survey and national vignette | In an earlier paper by our group [1] we presented statistical analysis based on 30 years of ACT data illustrating gender disparity in engineering majors and career choices. Obtained results also revealed the presence of a large number of students who are interested in engineering but who may not be ... | | 2012-01-01 |
114 |
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Stevens, Kenneth | Energy and performance models for synchronous and asynchronous communication | Communication costs, which have the potential to throttle design performance as scaling continues, are mathematically modeled and compared for various pipeline methodologies. First-order models are created for common pipeline protocols, including clocked flopped, clocked time-borrowing latch, async... | | 2010 |
115 |
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Harrison, Reid R. | Low-power FM transmitter for use in neural recording applications | We present a low power FM transmitter for use in neural recording telemetry. The transmitter consists of a low noise biopotential amplifier and a voltage controlled oscillator used to transmit the amplified neural signals at a frequency of 433 MHz. The circuit is powered through a transcutaneous,... | RF telemetry; Transmitter; Neural recording; Low power circuits; Multielectrode arrays; Voltage controlled oscillator (VCO) | 2004-01-01 |
116 |
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Harrison, Reid R. | Silicon implementation of the fly's optomotor control system | Flies are capable of stabilizing their body during free flight by using visual motion information to estimate self-rotation. We have built a hardware model of this optomotor control system in a standard CMOS VLSI process. The result is a small, low-power chip that receives input directly from the r... | Optomotor control system; photoreceptors; Insect visual system; Motion detector; CMOS transistor | 2000-01-01 |
117 |
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Smith, Kent F. | A fast parallel squarer based on divide-and-conquer | Fast and small squarers are needed in many applications such as image compression. A new family of high performance parallel squarers based on the divide-and-conquer method is reported. Our main result was realizing the basis cases of the divide-and-conquer recursion by using optimized n-bit primiti... | Squarer; Parallel squarers; Divide-and-conquer; MOPS; CMOS | 1995 |
118 |
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Harrison, Reid R. | CMOS imager with on-chip temporal filtering for motion pre-processing | Robust motion detection algorithms such as the motion energy model require temporal filtering at the pixel level. We have designed and tested a CMOS imager with integrated, pixel-level temporal filtering necessary for motion detection. This temporal filtering enhances transients and provides a ... | | 2002-01-01 |
119 |
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Ailion, David Charles | Low cost integrated circuit versatile pulse and frequency counter | In this paper we describe a compact multipurpose counter whose design is based on the use of plastic integrated circuits. The circuit contains about $90 worth of semiconductor components and is very easy to wire; nevertheless, it is extremely versatile. It consists of dual 107 and 106 counters which... | Integrated circuits; Counters; Physics instruments | 1969 |
120 |
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Tiwari, Ashutosh | Tb2O3 thin films: An alternative candidate for high-k dielectric applications | We are reporting the growth and structural, optical, and dielectric properties of Tb2O3, a relatively unexplored high-k dielectric material. A pulsed-laser deposition technique was used to grow Tb2O3 thin-films on four different substrates: Si(100), SrTiO3(100), LaAlO3(100), and MgO(100). High resol... | | 2014-01-01 |
121 |
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Planelles, Vicente | Method for obtaining an enriched population of sirna-expressing cells | Problems with transience of siRNA-mediated knock-down and transfection efficiency have limited the scope of RNAi-based experiments. The invention provides a tool for employing RNAi more efficiently and effectively by integrating RNAi expression with methods of cell enrichment. | | 2010 |
122 |
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Myers, Chris J. | Synthesis of timed asynchronous circuits | In this paper we present a systematic procedure to synthesize timed asynchronous circuits using timing constraints dictated by system integration, thereby facilitating natural interaction between synchronous and asynchronous circuits. In addition, our timed circuits also tend to be more &dent, in b... | | 1993 |
123 |
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Myers, Chris J. | Synthesis of timed asynchronous circuits | Abstract-In this paper we present a systematic procedure to synthesize timed asynchronous circuits using timing constraints dictated by system integration, thereby facilitating natural interaction between synchronous and asynchronous circuits. In addition, our timed circuits also tend to be more & d... | | 1993 |
124 |
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Stevens, Kenneth | Symbolic verification of timed asynchronous hardware protocols | Correct interaction of asynchronous protocols re- quires verification. Timed asynchronous protocols add another layer of complexity to the verification challenge. A methodology and automated tool flow have been developed for verifying systems of timed asynchronous circuits through compositional mode... | | 2013-01-01 |
125 |
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Myers, Chris J. | Direct synthesis of timed asynchronous circuits | This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a deterministic graph specification with timing constraints. A timing analysis extracts the timed concurrency and timed cau... | | 1999 |