Filters: School Or College: "College of Engineering" Department: "Computing, School of" Collection: "ir_uspace"
| Creator | Title | Description | Subject | Date | ||
|---|---|---|---|---|---|---|
| 76 |
 |
Davis, Al | Automating the design of embedded domain specific accelerators | Domain specific architecture (DSA) design currently involves a lengthy process that requires significant designer knowledge, experience, and time in arriving at a suitable code generator and architecture for the target application suite. Given the stringent time to market constraints and the dyna... | Domain specific architecture; Stall cycle analysis; SCA; Domain specific accelerators | 2008 |
| 77 |
 |
Richardson, William F.; Brunvand, Erik L. | The NSR processor prototype | The NSR Non Synchronous RISC processor is a general purpose processor structured as a collection of self timed units that operate concurrently and communicate over bundled data channels in the style of micropipelines?? These units correspond to standard synchronous pipeline stages such as Instr... | Self-timed Systems; Asynchronous systems; Micropipelines; FPGAs; RISC processor | 1992 |
| 78 |
 |
Regehr, John | Operating system support for multimedia: the programming model matters | Multimedia is an increasingly important part of the mix of applications that users run on personal computers and workstations. The requirements placed on a multimedia operating system are demanding and often conflicting: untrusted, independently written soft real-time applications must be able to co... | 2000-01-01 | |
| 79 |
 |
Freire, Juliana; Silva, Claudio T. | Querying and creating visualizations by analogy | While there have been advances in visualization systems, particularly in multi-view visualizations and visual exploration, the process of building visualizations remains a major bottleneck in data exploration. We show that provenance metadata collected during the creation of pipelines can be reused ... | Provenance; VisTrails; Pipelines; Query-by-example | 2007-11 |
| 80 |
 |
Yang, Yue; Gopalakrishnan, Ganesh; Lindstrom, Gary E. | Rigorous concurrency analysis of multithreaded programs | This paper explores the practicality of conducting program analysis for multithreaded software using constraint solv- ing. By precisely defining the underlying memory consis- tency rules in addition to the intra-thread program seman- tics, our approach orders a unique advantage for program ver- ... | Concurrency analysis; Multithreaded programs | 2003 |
| 81 |
 |
Fujimoto, Richard M. | The roll back chip: hardware support for distributed simulation using time warp | Distributed simulation offers an attractive means of meeting the high computational demands of discrete event simulation programs. The Time Warp mechanism has been proposed to ensure correct sequencing of events in distributed simulation programs without blocking processes unnecessarily. However, th... | Roll back chip; Distributed simulation; Discrete event; Simulation programs; Time Warp mechanism | 1987 |
| 82 |
 |
Hibler, Michael J. | Using annotated interface definitions to optimize RPC | In RPC-based communication, it is useful to distinguish the RPC interface, which is the "network contract" between the client and the server, from the presentation, which is the "programmer's contract" between the RPC stubs and the code that calls or is called by them. Presentation is usually a fixe... | annotated interface definitions; RPC-based communication | 1995 |
| 83 |
 |
Freire, Juliana; Silva, Claudio T. | VisComplete: automating suggestions for visualization pipelines | Building visualization and analysis pipelines is a large hurdle in the adoption of visualization and workflow systems by domain scientists. In this paper, we propose techniques to help users construct pipelines by consensus-automatically suggesting completions based on a database of previously creat... | VisComplete; Workflows; Auto completion; Visualization pipelines | 2008-11 |
| 84 |
 |
Freire, Juliana; Silva, Claudio T. | VisMashup: streamlining the creation of custom visualization applications | Visualization is essential for understanding the increasing volumes of digital data. However, the process required to create insightful visualizations is involved and time consuming. Although several visualization tools are available, including tools with sophisticated visual interfaces, they are o... | VisMashup; Dataflow; Visualization systems; Mashups; Medleys | 2009-11 |
| 85 |
 |
Lindstrom, Gary E. | ETYMA: a framework for modular systems | Modularity, i.e. support for the flexible construction, adaptation, and combination of units of software, is an important goal in many systems. In most cases, however, systems achieve only a few aspects of modularity. The problem can be traced to the inflexibility, or the limited view of modularity ... | ETYMA; Modularity; Modular systems | 1994 |
| 86 |
 |
Evans, David | Graphical man/machine communications: December 1972 | The object of the graphical man/machine communication effort is the development of computers and computing techniques the people may use interactively in real time to extend their problem-solving capability, and to work cooperatively by means of improved communications via computer. This report summ... | Waveform processing; Symbolic computation; Man/machine communications | 1972-12 |
| 87 |
 |
Balasubramonian, Rajeev | Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures | Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper we propose a cache and TLB layout and design that leverages repeater insertion to provide dynamic low-cost configurability trading of size and speed on a per application ... | Translation lookaside buffer (TLB) | 2000 |
| 88 |
 |
Carter, John B. | MP-LOCKs: Replacing hardware synchronization primitives with message passing | Shared memory programs guarantee the correctness of concurrent accesses to shared data using interprocessor synchronization operations. The most common synchronization operators are locks, which are traditionally implemented in user-level libraries via a mix of shared memory accesses and hardware sy... | MP-LOCKs; Message passing; Shared memory programs; Synchronization operators; Synchronization primitives | 2011-05 |
| 89 |
 |
Balasubramonian, Rajeev | Power efficient resource scaling in partitioned architectures through dynamic heterogeneity | The ever increasing demand for high clock speeds and the desire to exploit abundant transistor budgets have resulted in alarming increases in processor power dissipation. Partitioned (or clustered) architectures have been proposed in recent years to address scalability concerns in future billion-tr... | Partitioned architectures; Clustered architectures; Energy × Delay2, Temperature; Dynamic frequency scaling; Thermal emergency | 2006 |
| 90 |
 |
Regehr, John | Scheduling Tasks with mixed preemption relations for robustness to timing faults | This paper introduces and shows how to schedule two novel scheduling abstractions that overcome limitations of existing work on preemption threshold scheduling. The abstractions are task clusters, groups of tasks that are mutually non-preemptible by design, and task barriers, which partition the tas... | 2002-01-01 | |
| 91 |
 |
Johnson, Christopher R. | Construction of a human torso model from magnetic resonance images for problems in computational electrocardiography | Applying mathematical models to real situations often requires the use of discrete geometrical models of the solution domain. In some cases destructive measurement of the objects under examination is acceptable, but in biomedical applications the measurements come from imaging techniques such as X-r... | Human torso model; MRI | 1994 |
| 92 |
 |
Balasubramonian, Rajeev | Dynamically managing the communication-parallelism trade-off in future clustered processors | Clustered microarchitectures are an attractive alternative to large monolithic superscalar designs due to their potential for higher clock rates in the face of increasingly wire-delay-constrained process technologies. As increasing transistor counts allow an increase in the number of clusters, th... | Clustered architectures; Microarchitecture; Decentralized cache; Interconnects | 2003 |
| 93 |
 |
Carter, John B. | Evaluating the potential of programmable multiprocessor cache controllers | The next generation of scalable parallel systems (e.g., machines by KSR, Convex, and others) will have shared memory supported in hardware, unlike most current generation machines (e.g., offerings by Intel, nCube, and Thinking Machines). However, current shared memory architectures are constrained b... | Programmable multiprocessor cache controllers; Scalable parallel systems; Shared memory | 1994 |
| 94 |
 |
Evans, David | Graphical man/machine communications: December 1971 | Semi-Annual Technical Report for period 1 June 1971 to 31 December 1971. This document includes a summary of research activities and facilities at the University of Utah under Contract F30602-70-C-0300. Information conveys important research milestones attained during this period by each of the f... | Man/machine communications; Computing systems; Digital waveform processing | 1971-12 |
| 95 |
 |
Balasubramonian, Rajeev | Integrating adaptive on-chip storage structures for reduced dynamic power | Energy efficiency in microarchitectures has become a necessity. Significant dynamic energy savings can be realized for adaptive storage structures such as caches, issue queues, and register files by disabling unnecessary storage resources. Prior studies have analyzed individual structures and their... | Microarchitecture | 2002 |
| 96 |
 |
Balasubramonian, Rajeev | Scalable, reliable, power-efficient communication for hardware transactional memory | In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true for a large-scale distributed memory system where multiple transactions may attempt to commit simultaneously and co-ordin... | Hardware; Transactional memory; Communication | 2008 |
| 97 |
 |
Yang, Yue; Gopalakrishnan, Ganesh; Lindstrom, Gary E. | A generic operational memory model specification framework for multithreaded program verification | Given the complicated nature of modern architectural and language level memory model designs, it is vital to have a systematic ap- proach for specifying memory consistency requirements that can support verification and promote understanding. In this paper, we develop a spec- ification methodolog... | Multithreaded program verification | 2003 |
| 98 |
 |
Sobh, Tarek M. | A graphical environment and applications for discrete event and hybrid systems in robotics and automation | In this paper we present an overview for the development of a graphical environment for simulating, analyzing, synthesizing, monitoring, and controlling complex discrete event and hybrid systems within the robotics, automation, and intelligent system domain. We start by presenting an overview of di... | Intelligent system domain; Graphical environment | 1994 |
| 99 |
 |
Seeley, Donn | A tour of the worm | On the evening of November 2, 1988, a self-replicating program was released upon the Internet 1. This program (a worm) invaded VAX and Sun-3 computers running versions of Berkeley UNIX, and used their sources to attack still more computers2. Within the space of hours this program had spread aacross ... | Computer worm | 1989 |
| 100 |
 |
Bruderlin, Beat | DI - An object-oriented user interface toolbox for modula-2 applications | The DI dialog interface tool library for Modula-2 applications described in this paper facilitates the design and implementation of graphical, object-oriented user interfaces for workstations with a graphical screen, a mouse and a keyboard. Much emphasis is put on the portability of the application... | DI dialog interface tool | 1990 |