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Filters: School Or College: "College of Engineering" Department: "Computing, School of" Collection: "ir_uspace"
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CreatorTitleDescriptionSubjectDate
351 Bruderlin, BeatA new approach to tolerance analysisTolerance analysis is seen as part of a more general problem, namely handling data with uncertainty. Uncertain geometric data arises when interpreting measured data, but also in solid modeling where floating point approximations are common, when representing design tolerances, or when dealing with l...Tolerance analysis1994
352 Johnson, Christopher R.Construction of a human torso model from magnetic resonance images for problems in computational electrocardiographyApplying mathematical models to real situations often requires the use of discrete geometrical models of the solution domain. In some cases destructive measurement of the objects under examination is acceptable, but in biomedical applications the measurements come from imaging techniques such as X-r...Human torso model; MRI1994
353 Sobh, Tarek M.Modeling and recovering uncertainties in sense dataThis work examines closely the possibilities for errors, mistakes and uncertainties in sensing systems. We identify and suggest techniques for modeling, analyzing, and recovering these uncertainties. This work concentrates on uncertainties in visual sensing to recover 3-D structure and motion charac...Uncertainties; Sensing systems; Visual sensing1994
354 Bruderlin, BeatSketching as a solid modeling toolThis paper describes 'Quick-sketch', a 2-d and 3d modeling tool for pen based computers. Users of this system define a model by simple pen strokes drawn directly on the screen of a pen-based PC. Lines, circles, arcs, or B-spline curves are automatically distinguished and interpreted from these strok...Quick-sketch; Modeling tool; Pen based computers; Computer sketching1994
355 Carter, John B.Reducing consistency traffic and cache misses in the avalanche multiprocessorFor a parallel architecture to scale effectively, communication latency between processors must be avoided. We have found that the source of a large number of avoidable cache misses is the use of hardwired write-invalidate coherency protocols, which often exhibit high cache miss rates due to exces...Consistency traffic; Cache misses; Parallel architecture; Communication latency1995
356 Hansen, Charles D.Massively parallel visualization: parallel renderingThis paper presents rendering algorithms, developed for massively parallel processors (MPPs), for polygonal, spheres, and volumetric data. The polygon algorithm uses a data parallel approach whereas the sphere and volume renderer use a MIMD approach. Implementations for these algorithms are presente...Parallel visualization; Parallel rendering; Massively parallel processors1995
357 Hibler, Michael J.Separating presentation from interface in RPC and IDLsIn RPC-based communication, we term the interface the set of remote procedures and the types of their arguments; the presentation is the way these procedures and types are mapped to the target language environment in a particular client or server, including semantic requirements. For example, pres...RPC-based communication; IDL; Presentation; Interface1995
358 Stoller, Leigh B.PPE interface and functional specificationThis document describes the interface and functional specification of a Protocol Processing Engine (PPE) for workstation clusters. The PPE is intended to provide the support necessary to implement low latency protocols requiring only low resource (cpu and bus bandwidth) consumption.Protocol Processing Engine; PPE; Workstation clusters1995
359 Brunvand, Erik L.A partial scan methodology for testing self-timed circuitsThis paper presents a partial scan method for testing control sections of macromodule based self-timed circuits for stuck-at faults. In comparison with other proposed test methods for self-timed circuits, this technique offers better fault coverage than methods using self-checking techniques, and ...1995
360 Brunvand, Erik L.Precise exception handling for a self-timed processorSelf-timed systems structured as multiple concurrent processes and communicating through self-timed queues are a convenient way to implement decoupled computer architectures. Machines of this type can exploit instruction level parallelism in a natural way, and can be easily modified and extended...1995
361 Henderson, Thomas C.Evolutionary teleomorphologyThe physical layout of organs and neural structures in biological systems is important to their functioning, and is the result of evolutionary selection forces. We believe this is true even at the individual neuron level, and should be accounted for in any bio-based approach. In particular, when tr...Evolutionary teleomorphology; Bio-based approach; Physical layout problem; PLP; Neurons; Nodes1995
362 Lindstrom, Gary E.Layered, server-based support for Object-Oriented application developmentThis paper advocates the idea that the physical modularity (file structure) of application components supported by conventional OS environments can be elevated to the level of logical modularity, which in turn can directly support application development in an object-oriented manner. We demonstrate ...Object-Oriented application development1995
363 Richardson, William F.Fred: an architecture for a self-timed decoupled computerDecoupled computer architectures provide an effective means of exploiting instruction level parallelism. Self-timed micropipeline systems are inherently decoupled due to the elastic nature of the basic FIFO structure, and may be ideally suited for constructing decoupled computer architectures. Fred ...Decoupled computer; Fred1995
364 Sobh, Tarek M.Sensor-based distributed control scheme for mobile robotsIn this paper we present a sensor-based distributed control scheme for mobile robots. This scheme combines centralized and decentralized control strategies. A server-client model is used to implement this scheme where the server is a process that caries out the commands to be executed, and each clie...Sensor-based; Distributed control scheme1995
365 Brunvand, Erik L.Testing self-timed circuits using partial scanThis paper presents a partial scan method for testing both the control and data path parts of macromodule based self-timed circuits for stuck-at faults. Compared with other proposed test methods for testing control paths in self-timed circuits, this technique offers better fault coverage under a st...1995
366 Carter, John B.; Davis, Al; Kuramkote, Ravindra; Stoller, Leigh B.Avalanche: A communication and memory architecture for scalable parallel computingAs the gap between processor and memory speeds widens?? system designers will inevitably incorpo rate increasingly deep memory hierarchies to maintain the balance between processor and memory system performance At the same time?? most communication subsystems are permitted access only to main m...Avalanche; Communication architecture; Memory architecture1995
367 Hibler, Michael J.Using annotated interface definitions to optimize RPCIn RPC-based communication, it is useful to distinguish the RPC interface, which is the "network contract" between the client and the server, from the presentation, which is the "programmer's contract" between the RPC stubs and the code that calls or is called by them. Presentation is usually a fixe...annotated interface definitions; RPC-based communication1995
368 Hansen, Charles D.Binary-swap and shear-warp volume renderer on the T3DLarge parallel machines give today's scientists the ability to compute very large simulations which may generate equally large data. Not only does having visualization tools on the parallel system allow the scientist to take advantage of the large memory to visualize the data, the processing power a...Volume rendering; Binary-swap1995
369 Richardson, William F.The Fred VHDL ModelThis is the companion document to my dissertation. It contains 47 pages of schematics, and 163 pages of VHDL code. It is pretty meaningless without the dissertation, and it only exists because I felt that I should archive this information somewhere.1995
370 Hansen, Charles D.Binary-swap volumetric rendering on the T3DThis paper presents a data distributed parallel raytraced volume rendering algorithm and its implementation on the CRI T3D. This algorithm distributes the data and the computational load to individual processing units to achieve fast and high-quality rendering of high-resolution data. The volume dat...Volume rendering; Binary-swap; Ray tracing; Parallel rendering1995
371 Gopalakrishnan, GaneshExplicit-enumeration based verification made memory-efficientWe investigate techniques for reducing the memory requirements of a model checking tool employing explicit enumeration. Two techniques are studied in depth: (1) exploiting symmetries in the model, and (2) exploiting sequential regions in the model. The first technique resulted in a significant reduc...Verification; Model checking tool; Memory-efficient1995
372 Hansen, Charles D.Cost-effective data-parallel load balancingLoad balancing algorithms improve a program's performance on unbalanced datasets, but can degrade performance on balanced datasets, because unnecessary load redistributions occur. This paper presents a cost-effective data-parallel load balancing algorithm which performs load redistributions only...Load balancing1995
373 Gopalakrishnan, GaneshTiming constraints for high speed counterflow-clocked pipeliningWith the escalation of clock frequencies and the increasing ratio of wire- to gate-delays, clock skew is a major problem to be overcome in tomorrow's high-speed VLSI chips. Also, with an increasing number of stages switching simultaneously comes the problem of higher peak power consumption. In our ...Timing constraints; clock frequencies; clock skew; high-speed; VLSI chips; counterflow-clocked pipelining1995
374 Carter, John B.Avalanche: A communication and memory architecture for scalable parallel computingAs the gap between processor and memory speeds widens, system designers will inevitably incorporate increasingly deep memory hierarchies to maintain the balance between processor and memory system performance. At the same time, most communication subsystems are permitted access only to main memory ...Avalanche; Computer memory; Memory architecture1995
375 Lindstrom, Gary E.Object-oriented programming in scheme with first-class modules and operator-based inheritanceWe characterize object-oriented programming as structuring and manipulating a uniform space of first-class values representing modules, a distillation of the notion of classes. Operators over modules individually achieve effects such as encapsulation, sharing, and static binding. A variety of idioms...First-class modules; Operator-based inheritance1995
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