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Creator | Title | Description | Subject | Date |
| 301 |
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Warnock, John E. | A hidden line algorithm for halftone picture representation | In exploring applications in computer graphics, one finds quickly that the representation of three dimensional objects in picture form is both a desirable and necessary capability. Applications dealing with any form of spatial design or with visual environment simulation need the ability to represen... | Halftone picture representation; Spatial design | 1968 |
| 302 |
 |
Bruderlin, Beat | An interactive N-Dimensional constraint system | In this paper, we present a graph-based approach to geometric constraint solving. Geometric primitives (points, lines, circles, planes, etc.) possess intrinsic degrees of freedom in their embedding space. Constraints reduce the degrees of freedom of a set of objects. A constraint graph is created wi... | Geometric constraint solving | 1994 |
| 303 |
 |
Bruderlin, Beat | Detecting ambiguities: an optimistic approach to robustness problems in computational geometry | Computational geometry algorithms deal with geometric objects, usually represented by coordinates in an n-dimensional Euclidean space. Most efficient algorithms implement geometric operations as floating point arithmetic operations on the coordinates. Since floating point numbers can only approxima... | Ambiguities; Computational geometry; Robustness problems | 1990 |
| 304 |
 |
Brunvand, Erik L. | A partial scan methodology for testing self-timed circuits | This paper presents a partial scan method for testing control sections of macromodule based self-timed circuits for stuck-at faults. In comparison with other proposed test methods for self-timed circuits, this technique offers better fault coverage than methods using self-checking techniques, and ... | | 1995 |
| 305 |
 |
Carter, Tony M. | Cascade: hardware for high/variable precision arithmetic | The Cascade hardware architecture for high/variable precision arithmetic is described. It uses a radix-16 redundant signed-digit number representation and directly supports single or multiple precision addition, subtraction, multiplication, division, extraction of the square root and computation... | | 1989 |
| 306 |
 |
Organick, Elliott I. | Semiannual technical report transformation of ADA programs into silicon (1 Sept. 1981- 28 Feb. 1982) | This report summarizes the first six months work of the research project, "Transformation of Ada Programs into Silicon." Our project has five main objectives: 1. Develop and document elements of a transformation methodology for converting Ada programs, or program constructs, into VLSI systems which ... | ADA programs; VLSI | 1982 |
| 307 |
 |
Freire, Juliana | Integrated scientific workflow management for the Emulab network testbed | The main forces that shaped current network testbeds were the needs for realism and scale. Now that several testbeds support large and complex experiments, management of experimentation processes and results has become more difficult and a barrier to high-quality systems research. The popularity o... | Workflow management; Data exploration; Emulab; Network testbeds | 2006 |
| 308 |
 |
Shirley, Peter S.; Gooch, Bruce | Artistic vision: painterly rendering using computer vision techniques | We present a method that takes a raster image as input and produces a painting-like image composed of strokes rather than pixels. Unlike previous automatic painting methods, we attempt to keep the number of brush-stroke small. This is accomplished by first segmenting the image into features, finding... | Painting-like image; Raster image; Painterly rendering | 2000 |
| 309 |
 |
Henderson, Thomas C. | A study of Pierce's group generator | Pierce describes an approach to map learning with uninterpreted sensors and effectors. As part of that, he describes a sensor grouping generator operator that attempts to arrange similar sensors into groups. Here we review that work and place it in a more strenuous statistical validation framewor... | Pierce's group; Map learning; Sensor grouping generator | 2010 |
| 310 |
 |
Brunvand, Erik L. | Precise exception handling for a self-timed processor | Self-timed systems structured as multiple concurrent processes and communicating through self-timed queues are a convenient way to implement decoupled computer architectures. Machines of this type can exploit instruction level parallelism in a natural way, and can be easily modified and extended... | | 1995 |
| 311 |
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Hansen, Charles D. | Flow charts: visualization of vector fields on arbitrary surfaces | We introduce a novel flow visualization method called Flow Charts, which uses a texture atlas approach for the visualization of flows defined over curved surfaces. In this scheme, the surface and its associated flow are segmented into overlapping patches, which are then parameterized and packed in ... | | 2008-09 |
| 312 |
 |
Orr, Douglas B. | OMOS - An object server for program execution | The benefits of object-oriented programming are well known, but popular operating systems provide very few object-oriented features to users, and few are implemented using object-oriented techniques themselves. In this paper we discuss a mechanism for applying object-oriented programming concepts to... | OMOS; Object server | 1992 |
| 313 |
 |
Davis, Alan L. | Data driven nets: a maximally concurrent, procedural, parallel process representation for distributed control systems | A procedural parallel process representation, known as data-driven nets is described. The sequencing mechanism of the data-driven representation is based on the principle of data dependency. Operations are driven into action by the arrival of the required working set of input operands. Execution of ... | Data driven nets | 1978 |
| 314 |
 |
Kessler, Robert R. | Concurrent Scheme | This paper describes an evolution of the Scheme language to support parallelism with tight coupling of control and data. Mechanisms are presented to address the difficult and related problems of mutual exclusion and data sharing which arise in concurrent language systems. The mechanisms are tailored... | Concurrent Scheme; Parallelism | 1990 |
| 315 |
 |
Henderson, Thomas C. | Evolutionary teleomorphology | The physical layout of organs and neural structures in biological systems is important to their functioning, and is the result of evolutionary selection forces. We believe this is true even at the individual neuron level, and should be accounted for in any bio-based approach. In particular, when tr... | Evolutionary teleomorphology; Bio-based approach; Physical layout problem; PLP; Neurons; Nodes | 1995 |
| 316 |
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Grodstein, Joel | User's manual for the sisyphus simulation environment | This report describes how to create and simulate a design with Sisyphus. Inasmuch as Sisyphus is written in Symbolics-Lisp, some familiarity with both Lisp and with Symbolics computers is presumed. In addition, the concepts presented here presume an acquaintance with [3]. First, a disclaimer ? this... | Sisyphus; Simulation environment; Symbolics-Lisp; Symbolics computers | 1986 |
| 317 |
 |
Gopalakrishnan, Ganesh | Peephole optimization of asynchronous networks through process composition and burst-mode machine generation | In this paper we discuss the problem of improving the e ciency of macromodule networks generated through asynchronous high level synthesis We compose the behaviors of the modules in the sub network being optimized using Dill s trace theoretic operators to get a single behavioral description for ... | Macromodule networks; Peephole; Asynchronous networks | 1993 |
| 318 |
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Gopalakrishnan, Ganesh | Verifying a virtual component interface-based PCI bus wrapper using an LSC-based specification | Because of the high stakes involved in integrating externally developed intellectual property (IP) cores used in System on Chip (SOC) designs, methods and tool support for quick, easy, decisive standard compliance verification must be developed. Such methods and tools include formal standard spec... | System on Chip; SOC; Verification; PCI bus wrapper; LSC | 2002-01-22 |
| 319 |
 |
Balasubramonian, Rajeev | Microarchitectural techniques to reduce interconnect power in clustered processors | The paper presents a preliminary evaluation of novel techniques that address a growing problem - power dissipation in on-chip interconnects. Recent studies have shown that around 50% of the dynamic power consumption in modern processors is within on-chip interconnects. The contribution of interc... | Microarchitectural techniques; Interconnect power; Clustered processors; On-chip | 2004 |
| 320 |
 |
Riloff, Ellen M. | Exploiting strong syntactic heuristics and co-training to learn semantic lexicons | We present a bootstrapping method that uses strong syntactic heuristics to learn semantic lexicons. The three sources of information are appositives, compound nouns, and ISA clauses. We apply heuristics to these syntactic structures, embed them in a bootstrapping architecture, and combine them with... | Syntactic heuristics; Semantic lexicons; Bootstrapping method; Appositives; Compound nouns; ISA clauses; Co-training | 2002 |
| 321 |
 |
Henderson, Thomas C. | Knowledge-based 2-D vision system synthesis | A knowledge-based approach to computer vision provides the needed flexibility for performing recognition and inspection of objects in a complex environment. A system is described which uses knowledge about the environment, sensors, and performance requirements to construct a functional configuratio... | 2-D vision system | 1987 |
| 322 |
 |
Weinstein, David | Cache-rings for memory efficient isosurface construction | Processor speeds continue to increase at faster rates than memory speeds. As this performance gap widens, it becomes increasingly important to develop "memory-conscious" algorithms - programs that still optimize instruction count and algorithmic complexity, but that also integrate optimizations for ... | Processor speeds; Memory speeds; Computer memory; Cache-rings | 1997 |
| 323 |
 |
Lindstrom, Gary E. | Using a functional language and graph reduction to program multiprocessor machines or functional control of imperative programs | This paper describes an effective means for programming shared memory multiprocessors whereby a set of sequential activities are linked together for execution in parallel. The glue for this linkage is provided by a functional language implemented via graph reduction and demand evaluation. The full ... | shared memory multiprocessors; Programming; functional language; graph reduction; Demand evaluation | 1991 |
| 324 |
 |
Balasubramonian, Rajeev | CHOP: adaptive filter-based DRAM caching for CMP server platforms | As manycore architectures enable a large number of cores on the die, a key challenge that emerges is the availability of memory bandwidth with conventional DRAM solutions. To address this challenge, integration of large DRAM caches that provide as much as 5× higher bandwidth and as low as 1/3rd of... | CHOP; DRAM caching; CMP server platforms; Manycore architectures; Hot page; Filter cache; Multi-core processors | 2010 |
| 325 |
 |
Sobh, Tarek M.; Henderson, Thomas C. | A dynamic recursive structure for intelligent exploration | We suggest a new approach for inspection and reverse engineering applications. In particular, we investigate the use of discrete event dynamic systems (DEDS) to guide and control the active exploration and sensing of mechanical parts for industrial inspection and reverse engineering. We introduce dy... | Intelligent exploration; Discrete event dynamic systems; DEDS; Dynamic recursive finite state machines; DRFSM | 1992 |
