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CreatorTitleDescriptionSubjectDate
126 Silva, Claudio T.ISP: An optimal out-of-core image-set processing streaming architecture for parallel heterogeneous systemsImage population analysis is the class of statistical methods that plays a central role in understanding the development, evolution, and disease of a population. However, these techniques often require excessive computational power and memory that are compounded with a large number of volumetric inp...2012-01-01
127 Organick, Elliott I.CASL - A language for automating the implementation of computer architecturesThe computer Architecture Specification Language (CASL), described in this paper, is intended for use by computer architects CASL is a state machine description language especially useful for describing digital systems at the "register transfer" level and designed to meet the needs of the computer a...Computer Architecture Specification Language1979
128 Brunvand, Erik L.; Carter, JohnImpulse: building a smarter memory controllerImpulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through configurable physical address remapping. By remapping physical addresses, applications control how their data is ac...1999
129 Shapiro, Michael D.Genetic architecture of parallel armor plate reduction in threespine sticklebacksHow many genetic changes control the evolution of new traits in natural populations? Are the same genetic changes seen in cases of parallel evolution? Despite long-standing interest in these questions, they have been difficult to address, particularly in vertebrates. We have analyzed the genetic bas...Genetic changes; Plate number; Genetic mapping2004
130 Rahman, AowabinDeep recurrent neural networks for building energy predictionThis poster illustrates the development of a deep recurrent neural network (RNN) model using long-short-term memory (LSTM) cells to predict energy consumption in buildings at one-hour time resolution over medium-to-long term time horizons ( greater than or equal to 1 week).Machine learning; Energy; Building energy modeling; Deep learning; Recurrent neural networks; Prediction2017-01-13
131 Kessler, Robert R.Concurrent SchemeThis paper describes an evolution of the Scheme language to support parallelism with tight coupling of control and data. Mechanisms are presented to address the difficult and related problems of mutual exclusion and data sharing which arise in concurrent language systems. The mechanisms are tailored...Concurrent Scheme; Parallelism1990
132 Balasubramonian, RajeevTowards scalable, energy-efficient, bus-based on-chip networksIt is expected that future on-chip networks for many-core processors will impose huge overheads in terms of energy, delay, complexity, verification effort, and area. There is a common belief that the bandwidth necessary for future applications can only be provided by employing packet-switched netwo...On-chip networks; Multi-core computing; Bus-based; Energy efficient2010
133 De St Germain, John Davison; Parker, Steven G.; Johnson, Christopher R.Uintah parallelism infrastructure: a performance evaluation on the SGI origin 2000Uintah is a component-based visual problem solving environment (PSE) designed to specifically address the unique problems inherent in running massively parallel scientific computations on terascale computing platforms. In particular, development of the Uintah system is part of the C-SAFE [2] effort ...Uintah; Problem solving environment; Performance analysis; Parallelism; Origin 2000; C-SAFE2001
134 Henderson, Thomas C.Instrumented sensor system - practiceIn previous work, we introduced the notion of Instrumented Logical Sensor Systems (ILSS) that are derived from a modeling and design methodology [4, 2]. The instrumented sensor approach is based on a sensori-computational model which defines the components of the sensor system in terms of their func...Instrumented Logical Sensor Systems; ILSS1997
135 Efros, Alexei L.Sensor-based distributed control scheme for mobile robotsIn this paper we present a sensor-based distributed control scheme for mobile robots. This scheme combines centralized and decentralized control strategies. A server-client model is used to implement this scheme where the server is a process that caries out the commands to be executed, and each clie...Sensor-based; Distributed control scheme1995
136 Kessler, Robert R.Visual threads: the benefits of multithreading in visual programming languagesAfter working with the CWave visual programming language, we discovered that many of our target domains required the ability to define parallel computations within a program. CWave has a strongly hierarchical model of computation, so it seemed like adding the ability to take a part of the hierarchy ...Visual threads; multithreading; CWave1997
137 landesman test.pdfRail-volution 2005, September 8-10, 2005. Salt Lake City, Utah. Workshop Summaries.Transportation; Community development; Public transportation2006-11-10
138 Stevens, KennethComparing energy and latency of asynchronous and synchronous NoCs for embedded SoCsPower consumption of on-chip interconnects is a primary concern for many embedded system-on-chip (SoC) applications. In this paper, we compare energy and performance characteristics of asynchronous (clockless) and synchronous network on-chip implementations, optimized for a number of SoC designs. We...2010
139 Henderson, Thomas C.; Cohen, ElaineInnate theories as a basis for autonomous mental developmentSloman (in robotics), Chomsky and Pinker (in natural language), and others, e.g., Rosenberg (in human cooperative behavior) have proposed that some abstract theories relevant to cognitive activity are encoded genetically in humans. The biological advantages of this are (1) to reduce the learning ...Autonomous mental development2009
140 Witkowski, Alan; Neatrour, Anna; Myntti, Jeremy; McBride, BrianMassive newspaper migration - Moving 22 million records from CONTENTdm to SolphalUtah Digital Newspapers is a pioneering digital newspapers program at the University of Utah J. Willard Marriott Library. Recently, a small project team completed a successful migration away from CONTENTdm onto a home-grown system called Solphal, built using open-source applications. The migration p...Digital libraries; Systems migration2017
141 Carter, Tony M.Cascade: a hardware alternative to bignumsThe Cascade hardware architecture for high/variable precision arithmetic is described. It uses a radix-16 redundant signed-digit number representation and directly supports single or multiple precision addition, subtraction, multiplication, division, extraction of the square root and computation of ...Cascade hardware; Bignums; Precision arithmetic1989
142 Susarla, Sai R.; Carter, JohnDataStations: ubiquitous transient storage for mobile usersIn this paper, we describe DataStations, an architecture that provides ubiquitous transient storage to arbitrary mobile applications. Mobile users can utilize a nearby DataStation as a proxy cache for their remote home file servers, as a file server to meet transient storage needs, and as a platf...DataStations; Ubiquitous transient storage; Proxy cache2003-11-14
143 Balasubramonian, RajeevInterference aware cache designs for operating system executionLarge-scale chip multiprocessors will likely be heterogeneous. It has been suggested by several groups that it may be worthwhile to implement some cores that are specially tuned to execute common code patterns. One such common application that will execute on all future processors is of course the ...Interference aware; Cache designs; Off-loading2009
144 Regehr, JohnOffline compression for on-chip RAMWe present offline RAM compression, an automated source-to-source transformation that reduces a program's data size. Statically allocated scalars, pointers, structures, and arrays are encoded and packed based on the results of a whole-program analysis in the value set and pointer set domains. We tar...2007-01-01
145 Henderson, Thomas C.Workshop on multisensor integration in manufacturing automationMany people helped make the Workshop a success, but special thanks must be given to Howard Moraff for his support, and to Vicky Jackson for her efforts in making things run smoothly. Finally, thanks to Jake Aggarwal for helping to start the ball rolling.multisensor integration; manufacturing automation1987
146 Furse, Cynthia M.; Harrison, Reid R.Low-power STDR CMOS sensor for locating faults in aging aircraft wiringA CMOS sensor used to locate intermittent faults on live aircraft wires is presented. A novel architecture was developed to implement the Sequence Time Domain Reflectometry method on a 0.5- m integrated circuit. The sensor locates short or open circuits on active wires with an accuracy of +/-1 ft w...Aging aircraft wire; CMOS sensors; Fault detection; Pseudo-random noise; Reflectometry methods; Spread spectrum; Wire fault location2006-01-01
147 Harrison, Reid R.Low-power STDR CMOS sensor for locating faults in aging aircraft wiringA CMOS sensor used to locate intermittent faults on live aircraft wires is presented. A novel architecture was developed to implement the Sequence Time Domain Reflectometry method on a 0.5- m integrated circuit. The sensor locates short or open circuits on active wires with an accuracy of +/-1 ft w...CMOS sensor; Pseudo-random noise; Reflectometry Methods; Spread spectrum; Wire fault location; Time Domain Vernier (TDV) method2007-01
148 Stoller, Leigh B.Message passing support in the Avalanche widgetMinimizing communication latency in message passing multiprocessing systems is critical. An emerging problem in these systems is the latency contribution costs caused by the need to percolate the message through the memory hierarchy (at both sending and receiving nodes) and the additional cost of ma...Avalanche widget; Message passing; Cache coherence; Message copying; Cache miss rates; Computer memory1996
149 Stoller, Leigh B.Shared memory as a basis for conservative distributed architectural simulationThis paper describes experience in parallelizing an execution-driven architectural simulation system used in the development and evaluation of the Avalanche distributed architecture. It reports on a specific application of conservative distributed simulation on a shared memory platform. Various comm...Shared memory; Avalanche distributed architecture1977
150 Chatterjee, Niladrish; Balasubramonian, Rajeev; Davis, Alan L.Rethinking DRAM design and organization for energy-constrained multicoresDRAM vendors have traditionally optimized for low cost and high performance, often making design decisions that incur energy penalties. For example, a single conventional DRAM access activates thousands of bitlines in many chips, to return a single cache line to the CPU. The other bits may be access...DRAM power consumption; Data-center power; Multicore memory; Trapeze Interactive Poster2010-03-15
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