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CreatorTitleDescriptionSubjectDate
101 Henderson, Thomas C.; Sikorski, ChristopherComputational sensor networksWe propose Computational Sensor Networks as a methodology to exploit models of physical phenomena in order to better understand the structure of the sensor network. To do so, it is necessary to relate changes in the sensed variables (e.g., temperature) to the aspect of interest in the sensor netw...Computational sensor networks2007
102 De St Germain, John Davison; Morris, Alan H.; Parker, Steven G.Performance analysis integration in the Uintah software development cycleThe increasing complexity of high-performance computing environments and programming methodologies presents challenges for empirical performance evaluation. Evolving parallel and distributed systems require performance technology that can be flexibly configured to observe different events and associ...Uintah; Problem solving environment; Performance analysis; Parallelism; C-SAFE2003
103 Wright, KristinUsing reliable multicast for caching and collaboration within the world wide webThe World Wide Web has become an important medium for information dissemination. One model for synchronized information dissemination within the Web is webcasting in which data are simultaneously distributed to multiple destinations. The Web's traditional unicast client/server communication model su...caching; collaboration1999
104 Pryor, T. AllanDesign of a Knowledge-Driven HISBiomedical Informatics1987
105 Balasubramonian, RajeevDynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large cachesIn future multi-cores, large amounts of delay and power will be spent accessing data in large L2/L3 caches. It has been recently shown that OS-based page coloring allows a non-uniform cache architecture (NUCA) to provide low latencies and not be hindered by complex data search mechanisms. In this ...Page coloring; Shadow-memory addresses; Cache capacity allocation; Data/page migration; Last level caches; Non-uniform cache architectures (NUCA)2009-02
106 Fujimoto, Richard M.Efficient instruction level simulation of computersA technique for creating efficient, yet highly accurate, instruction level simulation models of computers is described. In contrast to traditional approaches that use a software interpreter, this technique employs direct execution of application programs on the host computer. An assembly language pr...Simulation models1987
107 Seyedhosseini Tarzjani, Seyed MojtabaImage segmentation with cascaded hierarchical models and logistic disjunctive normal networksContextual information plays an important role in solving vision problems such as image segmentation. However, extracting contextual information and using it in an effective way remains a difficult problem. To address this challenge, we propose a multi-resolution contextual framework, called cascade...2013-01-01
108 Sperry, John S.Anatomy of the palm Rhapis excelsa, IX. Xylem structure of the leaf insertionSTEMS OF PERENNIAL PLANTS, particularly trees, represent a considerable investment in biomass. Trees can survive even under the most adverse conditions, but only if the hydraulic integrity of the stem is preserved. A very important and vulnerable part of the stem is the xylem. As water is pulled int...Palm stems; Palm stem anatomy; Palm leaves; Leaf insertion; Vessel network; Vessel-length distribution; Primary vascular stem tissue; Hydraulic architechture; Water column1983
109 Johnson, Christopher R.Grid-enabling problem solving environments: a case study of SCIRun and NetSolveCombining the functionality of NetSolve, a grid-based middleware solution, with SCIRun, a graphically-based problem solving environment (PSE), yields a platform for creating and executing grid-enabled applications. Using this integrated system, hardware and/or software resources not previously ac...Grid computing; SCIRun; NetSolve; Problem solving environment; Numerical libraries; Parallel programming (Computer science)2001
110 Balasubramonian, RajeevOptimizing communication and capacity in a 3D stacked reconfigurable cache hierarchyCache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postulate a 3D chip design that stacks SRAM and DRAM upon processing cores and employs OS-based page coloring to minimize hori...Multi-core processors; Cache and memory hierarchy; Non-uniform cache architecture (NUCA); Page coloring; On-chip networks; SRAM/DRAM cache reconfiguration2009-02
111 Ricci, RobertA survey of computing migration2010-02-26
112 Li, Guodong; Gopalakrishnan, Ganesh; Kirby, Robert Michael IiPUG : A Symbolic Verifier of GPU ProgramsPUG is a automated verifier for GPU programs written in C/CUDA. PUG verifies GPU kernels for Data Races, Barrier mismatches, Totally wrong results, and Weak memory model related bugs. SMT-based correctness checking methods for these error are often more scalable, general and modular.2010-10-06
113 Balasubramonian, RajeevMicroarchitectural techniques to reduce interconnect power in clustered processorsThe paper presents a preliminary evaluation of novel techniques that address a growing problem - power dissipation in on-chip interconnects. Recent studies have shown that around 50% of the dynamic power consumption in modern processors is within on-chip interconnects. The contribution of interc...Microarchitectural techniques; Interconnect power; Clustered processors; On-chip2004
114 Hansen, Charles D.Semotus visum: a flexible remote visualization frameworkBy offering more detail and precision, large data sets can provide greater insights to researchers than small data sets. However, these data sets require greater computing resources to view and manage. Remote visualization techniques allow the use of computers that cannot be operated locally. The S...Remote visualization; Semotus Visum2002
115 Lindstrom, Gary E.Layered, server-based support for Object-Oriented application developmentThis paper advocates the idea that the physical modularity (file structure) of application components supported by conventional OS environments can be elevated to the level of logical modularity, which in turn can directly support application development in an object-oriented manner. We demonstrate ...Object-Oriented application development1995
116 Zhang, Lixin; Carter, JohnMemory system support for image processingProcessor speeds are increasing rapidly, but memory speeds are not keeping pace. Image processing is an important application domain that is particularly impacted by this growing performance gap. Image processing algorithms tend to have poor memory locality because they access their data in a non-se...Processor speeds; Memory system support; Memory speeds1999
117 Carter, John B.A comparison of software and hardware synchronization mechanisms for distributed shared memory multiprocessorsEfficient synchronization is an essential component of parallel computing. The designers of traditional multiprocessors have included hardware support only for simple operations such as compare-and-swap and load-linked/store-conditional, while high level synchronization primitives such as locks, bar...Hardware locks1996
118 Carter, John B.Evaluating the potential of programmable multiprocessor cache controllersThe next generation of scalable parallel systems (e.g., machines by KSR, Convex, and others) will have shared memory supported in hardware, unlike most current generation machines (e.g., offerings by Intel, nCube, and Thinking Machines). However, current shared memory architectures are constrained b...Programmable multiprocessor cache controllers; Scalable parallel systems; Shared memory1994
119 Regehr, JohnHierarchical schedulers, performance guarantees, and resource managementAn attractive approach to scheduling applications with diverse CPU scheduling requirements is to use different schedulers for different applications. For example: real-time schedulers allow applications to perform computations before deadlines, time-sharing schedulers provide high throughput for com...1999-01-01
120 Yamaguchi, AyakoRhythm generation, coordination, and initiation in the vocal pathways of male African clawed frogscentral pattern generator; vocalization; parabrachial area; hindbrain; bilateral coordination; motor programs2016
121 Freire, JulianaBridging the XML-relational divide with LegoDB: a demonstrationWe present LegoDB, a cost-based XML storage mapping engine that automatically explores a space of possible XML-to-relational mappings and selects an efficient mapping for a given application.LegoDB; Storage mappings2003
122 Mastrangelo, Carlos H.Design and characterization of electronic sensing system for a 13 × 13 biomechanical ground reaction sensor arrayThis paper presents the design and characterization of an electronic sensing system interfaced with a high-density flexible biomechanical ground reaction sensor array (GRSA). The prototype system can be incorporated into a personal boot heel to measure real-time ground force, shear strain and sole d...2013-01-01
123 Sperry, John S.Hydraulic architecture of palmsThe water transport and storage system of palms is adapted to maintain the primary stem xylem functional over the life of the shoot, and in spite of severe drought. However, our structural information far exceeds our knowledge of vascular function, and these functional considerations bring more que...Hydraulic architecture; Rhapis excelsa; Cavitation1995
124 Stevens, KennethCA-BIST for asynchronous circuits: a case study on the RAPPID asynchronous instruction length decoderThis paper presents a case study in low-cost noninvasive Built-In Self Test (BIST) for RAPPID, a largescale 120,000-transistor asynchronous version of the Pentium® Pro Instruction Length Decoder, which runs at 3.6 GHz. RAPPID uses a synchronous 0.25 micron CMOS library for static and domino lo...2000
125 Keller, Robert M.Rediflow architecture prospectusRediflow is intended as a multi-function (symbolic and numeric) multiprocessor, demonstrating techniques for achieving speedup for Lisp-coded problems through the use of advanced programming concepts, high-speed communication, and dynamic load-distribution, in a manner suitable for scaling to upward...Rediflow; Multi-function multiprocessors; Lisp-coded problems1985
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