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CreatorTitleDescriptionSubjectDate
51 Balasubramonian, RajeevA case for increased operating system support in chip multi-processorsWe identify the operating system as one area where a novel architecture could significantly improve on current chip multi-processor designs, allowing increased performance and improved power efficiency. We first show that the operating system contributes a non-trivial overhead to even the most com...2005
52 De St Germain, John Davison; Parker, Steven G.; Johnson, Christopher R.Uintah: a massively parallel problem solving environmentThis paper describes Uintah, a component-based visual problem solving environment (PSE) that is designed to specifically address the unique problems of massively parallel computation on terascale computing platforms. Uintah supports the entire life cycle of scientific applications by allowing scient...Uintah; Problem solving environment; Computational steering; Parallel computers2000
53 Carter, John B.Reducing consistency traffic and cache misses in the avalanche multiprocessorFor a parallel architecture to scale effectively, communication latency between processors must be avoided. We have found that the source of a large number of avoidable cache misses is the use of hardwired write-invalidate coherency protocols, which often exhibit high cache miss rates due to exces...Consistency traffic; Cache misses; Parallel architecture; Communication latency1995
54 Brunvand, Erik L.A case for increased operating system support in chip multi-processorsWe identify the operating system as one area where a novel architecture could significantly improve on current chip multi-processor designs, allowing increased performance and improved power efficiency. We first show that the operating system contributes a non-trivial overhead to even the most com...2005
55 Panangaden, PrakashVerification of systolic arrays: a stream functional approachWe illustrate that the verification of systolic architectures can be carried out using techniques developed in the context of verification of programs. This is achieved by a decomposition of the original problem into separately proving the correctness of the data representation and of the individual...Verification; systolic arrays; stream function1985
56 Gopalakrishnan, GaneshHierarchical action refinement: a methodology for compiling asynchronous circuits from a concurrent HDLA hardware specification formalism called hopCP is introduced, hopCP provides an uniform notation t o describe the causal relationships between a set of nonatomic actions which capture the computational, concurrency, control and communication aspects of hardware behavior. A systematic approach to sy...Hierarchical action refinement; Hardware specification formalism; hopCP1991
57 Clayton, Paul D.Building a Comprehensive Clinical Information System from Components: The Approach at Intermountain Health CareBiomedical Informatics2003
58 Gehl, Robert W.The archive and the processor: the internal logic of web 2.0In Web 2.0, there is a social dichotomy at work based upon and reflecting the underlying Von Neumann architecture of computers. In the hegemonic Web 2.0 business model, users are encouraged to process digital ephemera by sharing content, making connections, ranking cultural artifacts, and producing ...2011
59 Balasubramonian, RajeevInterconnect-aware coherence protocols for chip multiprocessorsImprovements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future billion transistor architectures due to their low design complexity, high clock frequency, and high throughput. In a...Interconnects; Chip multiprocessors; Coherence2006
60 Balasubramonian, RajeevLeveraging wire properties at the microarchitecture levelIn future microprocessors, communication will emerge as a major bottleneck. The authors advocate composing future interconnects of some wires that minimize latency, some that maximize bandwidth, and some that minimize power. A microarchitecture aware of these wire characteristics can steer on-chip ...Microarchitecture; Interconnects; Cache coherence2006-11
61 Frey, Lewis J.ca! - emergency and disaster recovery system extensions to caBIG™During Hurricane Katrina, US Federal and State Agencies had disparate data acquisition systems, separate data networks and unique incompatible applications. •System incompatibilities exist even between various Federal agencies. •Consistent data available to one agency should be available to an...caBIG; Data acquisition systems; Data sharing; Information sharing; Trapeze Interactive Poster2009-09-23
62 Balasubramonian, RajeevDynamically managing the communication-parallelism trade-off in future clustered processorsClustered microarchitectures are an attractive alternative to large monolithic superscalar designs due to their potential for higher clock rates in the face of increasingly wire-delay-constrained process technologies. As increasing transistor counts allow an increase in the number of clusters, th...Clustered architectures; Microarchitecture; Decentralized cache; Interconnects2003
63 Zhang, ChengqiangHardware-only stream prediction + cache prefetching + dynamic access orderingThe speed gap between processors and memory system is becoming the performance bottleneck for many applications, and computations with strided access patterns are among those that suffer most. The vectors used in such applications lack temporal and often spatial locality, and are usually too large t...Speed gap; Stream prediction; Cache prefetching; Dynamic access ordering1999
64 Mathew, Binu K.; Davis, Al; Fang, ZhenA Gaussian probability accelerator for SPHINX 3Accurate real-time speech recognition is not currently possible in the mobile embedded space where the need for natural voice interfaces is clearly important. The continuous nature of speech recognition coupled with an inherently large working set creates significant cache interference with other...Speech recognition; SPHINX 3; Speech recognizers2003-07-22
65 Hibler, Michael J.Microkernels meet recursive virtual machines (draft. May 10, 1996))This paper describes a novel approach to providing modular and extensible operating system functionality, and encapsulated environments, based on a synthesis of micro-kernel and virtual machine concepts. We have developed a virtualizable architecture that allows recursive virtual machines (virtual m...Microkernels; Virtual machines; Operating system functionality1996
66 Warner, Homer R.Enroute Toward a Computer-Based Patient Record: The ACIS ProjectBiomedical Informatics1995
67 Pryor, T. AllanA MLM-Based Order Entry System: The Use of Knowledge in a Traditional HIS ApplicationBiomedical Informatics1990
68 Balasubramonian, RajeevPower efficient resource scaling in partitioned architectures through dynamic heterogeneityThe ever increasing demand for high clock speeds and the desire to exploit abundant transistor budgets have resulted in alarming increases in processor power dissipation. Partitioned (or clustered) architectures have been proposed in recent years to address scalability concerns in future billion-tr...Partitioned architectures; Clustered architectures; Energy × Delay2, Temperature; Dynamic frequency scaling; Thermal emergency2006
69 Brunvand, Erik L.Practical advances in asynchronous design and in asynchronous/synchronous interfacesAsynchronous systems are being viewed as an increasingly viable alternative to purely synchronous systems. This paper gives an overview of the current state of the art in practical asynchronous circuit and system design in four areas: controllers, datapaths, processors, and the design of asynchr...1999
70 Love, April M.Hidden water: Salt Lake County, UT drainages, a part of the Western Waters Digital LibrarySalt Lake Valley watershed, hidden water2012
71 Normann, Richard A.; Jones, Kelly E.Advanced demultiplexing system for physiological stimulationA CMOS very large scale integration (VLSI) chip has been designed and built to implement a scheme developed for multiplexing/demultiplexing the signals required to operate an intracortical stimulating electrode array. Because the use of radio telemetry in a proposed system utilizing this chip may im...Electrode Array; Stimulation; Telemetry; Microelectrodes; Transistors1997
72 Balasubramonian, RajeevEnergy-efficient processor design using multiple clock domains with dynamic voltage and frequency scalingAs clock frequency increases and feature size decreases, clock distribution and wire delays present a growing challenge to the designers of singly-clocked, globally synchronous systems. We describe an alternative approach, which we call a Multiple Clock Domain (MCD) processor in which the chip is d...Multiple clock domains; Synchronization; Microarchitecture2002
73 Pascucci, ValerioExploring power behaviors and trade-offs of in-situ data analyticsAs scientific applications target exascale, challenges related to data and energy are becoming dominating concerns. For example, coupled simulation workflows are increasingly adopting in-situ data processing and analysis techniques to address costs and overheads due to data movement and I/O. However...2013-01-01
74 Balasubramonian, RajeevNDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloadsWhile Processing-in-Memory has been investigated for decades, it has not been embraced commercially. A number of emerging technologies have renewed interest in this topic. In particular, the emergence of 3D stacking and the imminent release of Micron's Hybrid Memory Cube device have made it more pra...2014-01-01
75 Carter, John B.The avalanche myrinet simulation packageThis is a user manual for version 2.0 of the Myrinet simulation package. Users of the V2.0 package can specify arbitrary network topologies composed of Myrinet switches with different number of ports. For example, 4-port and 32-port switches can be used in a single system. Because the V2.0 model sup...Avalanche Myrinet; Simulation Package; User manual; Myrinet switches; port switches1996
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