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CreatorTitleDescriptionSubjectDate
26 Myers, Chris J.Effcient verification of hazard-freedom in gate-level timed asynchronous circuitsThis paper presents an efficient method for verifying hazard freedom in timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that utilize explicit timing information fur optimization throughout the entire design process. In asynchronous circuits, correct operation require...2003
27 Myers, Chris J.Timed circuit verification using TEL structuresAbstract-Recent design examples have shown that significant performance gains are realized when circuit designers are allowed to make aggressive timing assumptions. Circuit correctness in these aggressive styles is highly timing dependent and, in industry, they are typically designed by hand. In ord...2001
28 Brunvand, Erik L.Automatic rapid prototyping of semi-custom VLSI circuits using actel FPGAsAbstract : We describe a technique for translating semi-custom VLSI circuits automatically into field programmable gate arrays (FPGAs) for rapid prototyping to develop a system. Using an array multiplier as an example of this translation, the VLSI circuits are designed using a cell-matrix based envi...1995
29 Smith, Kent F.Automatic rapid prototyping of semi-custom VLSI circuits using FPGAsWe describe a technique for translating semi-custom VLSI circuits automatically, integrating two design environments, into field programmable gate arrays (FPGAs) for rapid and inexpensive prototyping. The VLSI circuits are designed using a cell-matrix based environment that produces chips with densi...Semi-custom; VLSI circuits1994
30 Warner, Homer R.Dynamic Aortic Diameter Measurements in vivoBiomedical Informatics1967
31 Boehme, ChristophSpin-dependent recombination - an electronic readout mechanism for solid state quantum computersIt is shown that coherent spin motion of electron-hole pairs localized in band gap states of silicon can influence charge carrier recombination. Based on this effect, a readout concept for silicon based solid-state spin-quantum computers as proposed by Kane is suggested. The 31P quantum bit (qbit) i...Spin readout; qbit; Spin-dependent recombination2002-10
32 Stevens, KennethEnergy and performance models for clocked and asynchronous communicationParameterized first-order models for throughput, energy, and bandwidth are presented in this paper. Models are developed for many common pipeline methodologies, including clocked flopped, clocked time-borrowing latch protocols, asynchronous two-cycle, four-cycle, delay-insensitive, and source synch...2003
33 Ailion, David CharlesLow cost high linearity solid state digital double boxcarIn this article, we describe a digital solid state double boxcar of infinite holding time and very high linearity. It uses a Hewlett-Packard (HP2212 A-M3) voltage-to-frequency converter (VFC) whose output is accumulated on a running counter, thereby providing signal averaging with an infinite holdin...High linearity; Boxcar; Instruments, Physics1969
34 Brunvand, Erik L.A cell set for self-timed design using actel FPGAsAsynchronous or self-timed systems that do not rely on a global clock to keep system components synchronized can offer significant advantages over traditional clocked circuits in a variety of applications. However, these systems require that suitable self-timed circuit primitives are available for b...Self-timed systems; Actel field programmable gate arrays; FPGA1991
35 Dawson, KyleHigh-voltage-compatible fully depleted CCDsWe describe charge-coupled device (CCD) development activities at the Lawrence Berkeley National Laboratory (LBNL). Back-illuminated CCDs fabricated on 200-300 fxm thick, fully depleted, high-resistivity silicon substrates are produced in partnership with a commercial CCD foundry. The CCDs are full...Large Synoptic Survey Telescope; X-ray emission; XMM22352006
36 Khan, Faisal HabibCharacterization of aging process in power converters using spread spectrum time domain reflectometryThis paper aims to find a new technique to predict the state of health of power converters by characterizing the most vulnerable components in the converter without affecting the normal circuit operation. Spread spectrum time domain reflectometry (SSTDR) can detect most of the aged components inside...2012-01-01
37 Stevens, Kenneth; Myers, Chris J.Average-case optimized technology mapping of one-hot domino circuitsThis paper presents a technology mapping technique for optimizing the average-case delay of asynchronous combinational circuits implemented using domino logic and one-hot encoded outputs. The technique minimizes the critical path for common input patterns at the possible expense of making less commo...1998
38 Myers, Chris J.; Stevens, KennethAverage-case optimized technology mapping of one-hot domino circuits*This paper presents a technology mapping technique for optimizing the average-case delay of asynchronous combinational circuits implemented using domino logic and one-hot encoded outputs. The technique minimizes the critical path for common input patterns at the possible expense of making less commo...1998
39 Stevens, KennethAutomatic synthesis of fast, compact self-timed controlAn automated synthesis tool, called the Most Excellent Asynchronous Tool, or MEAT is presented. This tool has been used to specify and synthesize self-timed circuits for a fully self-timed 300,000 transistor communication co-processor. The Specification is done with stylized state diagrams. This is ...1992
40 Myers, Chris J.Stochastic cycle period analysis in timed circuitsThis paper presents a technique to estimate the stochastic cycle period (SCP), a performance metric for timed asynchronous circuits. This technique uses timed stochastic Petri nets (TSPN) which support choice and arbitrary delay distributions. The SCP is the delay of the average path in a TSPN when ...1999
41 Stevens, KennethLazy transition systems and asynchronous circuit synthesis with relative timing assumptionsThis paper presents a design flow for timed asynchronous circuits. It introduces lazy transitions systems as a new computational model to represent the timing information required for synthesis. The notion of laziness explicitly distinguishes between the enabling and the firing of an event in a tr...2002
42 Stevens, KennethModeling and verifying circuits using generalized relative timingWe propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not just a relative ordering between events, but also some forms of metric timing constraints. Circuits modeled using gener...2005
43 Davis, Alan L.Data driven nets: a maximally concurrent, procedural, parallel process representation for distributed control systemsA procedural parallel process representation, known as data-driven nets is described. The sequencing mechanism of the data-driven representation is based on the principle of data dependency. Operations are driven into action by the arrival of the required working set of input operands. Execution of ...Data driven nets1978
44 Jacobson, HansDesign and validation of a simultaneous multi-threaded DLX processorModern day computer systems rely on two forms of parallelism to achieve high performance, parallelism between individual instructions of a program (ILP) and parallelism between individual threads (TLP). Superscalar processors exploit ILP by issuing several instructions per clock, and multiprocessors...DLX processor; Validation1999
45 Khan, Faisal HabibUse of spread spectrum time domain reflectometry to estimate state of health of power convertersA new online measurement and analysis method has been presented in this paper to identify the state of health of power converter circuits. Using spread spectrum time domain reflectometry (SSTDR), impedance in the various current paths inside the converter as well as any fault can be identified witho...2012-01-01
46 Myers, Chris J.Interfacing synchronous and asynchronous modules within a high-speed pipeline*This paper describes a new technique for integrating asynchronous modules within CI high-speed synchronous pipeline. Our design eliminates potential metastability problems by using Q clock generated by Q stoppable rang oscillator, which is capable of driving the large clock load found in present d...1997
47 Khan, Faisal HabibDeriving new topologies of DC-DC converters featuring basic switching cellsThis paper will introduce the two basic switching cells, P-cell and N-cell, and their applications in different power electronic circuits. These basic cells have one switching element and one diode. The P-cell is the mirror circuit of the N-cell and vice-versa, and this paper suggests that any powe...DC-DC converters; P-cell; N-cell; Switching cells; Cúk converters2006-07
48 Brunvand, Erik L.; Smith, Kent F.A comparison of self-timed design using FPGA, CMOS, and GaAs technologiesAsynchronous or self-timed systems that do not rely on U global clock to keep system components synchronized can offer significant advantages over traditional clocked circuits in a variety of applications. One advantage is that because of the separation of timing, from, functionality in these sys...1992
49 Gopalakrishnan, GaneshSome unusual micropipeline circuitsWe present a few unusual Micropipelines (Sutherland, CACM, September 1989) that employ the Muller C-ELEMENT or an extension of the C-ELEMENT called LOCKC (Liebchen and Gopalakrishnan, ICCD, 1992). We first describe two variations of the two-dimensional Micropipeline structure realized using ordinary...Micropipeline circuits; Micropipelines1993
50 Stevens, KennethRelative timingRelative Timing is introduced as an informal method for aggressive asynchronous design. It is demonstrated on three example circuits (C-Element, FIFO, and RAPPID Tag Unit), facilitating transformations from speed-independent circuits to burst-mode, relative timed, and pulse-mode circuits. Relative ...1999
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