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CreatorTitleDescriptionSubjectDate
26 Keller, Robert M.; Lindstrom, Gary E.An architecture for a loosely-coupled parallel processorAn architecture for a large (e. g. 1000 processor) parallel computer is presented. The processors are loosely-coupled, in the sense that communication among them is fully asynchronous, and each processor is generally not unduly delayed by any immediate need for specific data values. The network supp...Loosely-coupled; Parallel processors1978
27 Brunvand, Erik L.Editorial asynchronous architectureAsynchronous design is enjoying a worldwide resurgence of interest following several decades in obscurity. Many of the early computers employed asynchronous design techniques, but since the mid 1970s almost all digital design has been based around the use of a central clock. The clock simplifies mos...1996-01-01
28 Davis, AlAutomating the design of embedded domain specific acceleratorsDomain specific architecture (DSA) design currently involves a lengthy process that requires significant designer knowledge, experience, and time in arriving at a suitable code generator and architecture for the target application suite. Given the stringent time to market constraints and the dyna...Domain specific architecture; Stall cycle analysis; SCA; Domain specific accelerators2008
29 Tasdizen, TolgaUsing sequential context for image analysisThis paper proposes the sequential context inference (SCI) algorithm for Markov random field (MRF) image analysis. This algorithm is designed primarily for fast inference on an MRF model, but its application requires also a specific modeling architecture. The architecture is composed of a sequence ...2010
30 Carter, John B.AS-COMA: An adaptive hybrid shared memory ArchitectureScalable shared memory multiprocessors traditionally use either a cache coherent nonuniform memory access (CC-NUMA) or simple cache-only memory architecture (S-COMA) memory architecture. Recently, hybrid architectures that combine aspects of both CC-NUMA and S-COMA have emerged. In this paper, we pr...AS-COMA; Hybrid shared memory1998
31 Fujimoto, Richard M.On synthesizing systolic arrays from recurrence equations with linear dependenciesWe present a technique for synthesizing systolic architectures from Recurrence Equations. A class of such equations (Recurrence Equations with Linear Dependencies) is defined and and the problem of mapping such equations onto a two dimensional architecture is studied. We show that such a mapping is ...Recurrence equations1986
32 Kumar, Sidharth; Pascucci, ValerioRemote visualizationGeneralized Architecture and pipeline for a remote site
33 Brunvand, Erik L.Precise exception handling for a self-timed processorSelf-timed systems structured as multiple concurrent processes and communicating through self-timed queues are a convenient way to implement decoupled computer architectures. Machines of this type can exploit instruction level parallelism in a natural way, and can be easily modified and extended...1995
34 Leither, LukeLibrary alchemy: researching contemporary artThis poster was created to present a workshop for researching contemporary art in the Marriott Library. The workshop and poster was created by Luke Leither, the Art and Architecture Library at the University of Utah.Art; Contemporary Art; Research; Fine Arts2013
35 Frey, Lewis J.Enhancing caBIG™ workflow for multi-tier distributionIntroduction caBIG™ Integration caBIG™ provides a GRID based application environment with data abstraction and vocabulary services, workflow management and a security framework. Sensor Abstraction Interface It is proposed to provide a sensor abstraction interface, using caDSR, enabling caBIG...caBIG; Sensor abstraction interface; Multi-tier distribution; Trapeze Interactive Poster2009
36 Cotter, Neil E.Generality Vs. speed of convergence in the cart-pole balancerThis paper compares the speed of convergence to an optimal solution of four controllers for the problem of balancing a pole on a cart. We demonstrate that controllers whose design is tailored specifically to the cart-pole problem (i.e. less general) converge more rapidly to an optimal solution. How...Cart-pole balancer; Generality; Speed of convergence1991
37 Lindstrom, Gary E.ETYMA: a framework for modular systemsModularity, i.e. support for the flexible construction, adaptation, and combination of units of software, is an important goal in many systems. In most cases, however, systems achieve only a few aspects of modularity. The problem can be traced to the inflexibility, or the limited view of modularity ...ETYMA; Modularity; Modular systems1994
38 Balasubramonian, RajeevMicroarchitectural wire management for performance and power in partitioned architecturesFuture high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low power. In such architectures, inter-partition communication over global wires has a significant impact on overall proc...Microarchitecture; Partitioned architectures; Heterogeneous interconnects; Cache access2005
39 Stevens, KennethA single chip low power asynchronous implementation of an FFT algorithm for space applicationsA fully asynchronous _x000C_fixed point FFT processor is introduced for low power space applications. The architecture is based on an algorithm developed by Suter and Stevens specifi_x000C_cally for a low power implementation. The novelty of this architecture lies in its high localization of compo...1998
40 Balasubramonian, RajeevUnderstanding the impact of 3D stacked layouts on ILP3D die-stacked chips can alleviate the penalties imposed by long wires within micro-processor circuits. Many recent studies have attempted to partition each microprocessor structure across three dimensions to reduce their access times. In this paper, we implement each microprocessor structure on a s...2007-01-01
41 Carter, Tony M.Cascade: hardware for high/variable precision arithmeticThe Cascade hardware architecture for high/variable precision arithmetic is described. It uses a radix-16 redundant signed-digit number representation and directly supports single or multiple precision addition, subtraction, multiplication, division, extraction of the square root and computation...1989
42 Carter, John B.Avalanche: A communication and memory architecture for scalable parallel computingAs the gap between processor and memory speeds widens, system designers will inevitably incorporate increasingly deep memory hierarchies to maintain the balance between processor and memory system performance. At the same time, most communication subsystems are permitted access only to main memory ...Avalanche; Computer memory; Memory architecture1995
43 Drews, Frank; Bermudez, Julio Cesar; Agutter, James A.; Foresti, Stefano A.; Westenskow, Dwayne R.; Syroid, Noah Daniel; Tashjian, ElizabethBetween art, science and technology: data representation architectureAs our civilization continues to dive deeper into the information age, making sense of complex data becomes critical. This work takes on this challenge by means of a novel method based on complete interdisciplinarity, design process and built-in evaluations. The result is the design, construction, ...Data representation; Visualization design; Data environments2005
44 Elens, Robert N.Sequencing computational events in heterogeneous distributed systemsDistributed systems are growing in number, size, and complexity. Some technological advances have been made to program these systems, most notably the remote procedure call. However, the nature of heterogeneous distributed systems allows for much more complex interactions and new programming techno...Sequencing; Computational events; Heterogeneous distributed systems1990
45 Brunvand, Erik L.Estimating performance of an ray- tracing ASIC designRecursive ray tracing is a powerful rendering technique used to compute realistic images by simulating the global light transport in a scene. Algorithmic improvements and FPGA-based hardware implementations of ray tracing have demonstrated realtime performance but hardware that achieves performance ...2006
46 Brunvand, Erik L.The NSR processorThe NSR (Non-Synchronous RISC) processor is a general-purpose computer structured (IS U collection of self-timed blocks that operate concurrently and communicate over bundled data channels in the style of micropipelines [3, 16]. These blocks correspond to standard synchronous pipeline stages such ...1993
47 Hibler, Michael J.The flask security architecture: system support for diverse security policiesOperating systems must be flexible in their support for security policies, i.e., the operating system must provide sufficient mechanisms for supporting the wide variety of real-world security policies. Systems claiming to provide this support have failed to do so in two ways: they either fail to pro...Flask; Security architecture1998
48 Carter, John B.Analysis of avalanche's shared memory architectureIn this paper, we describe the design of the Avalanche multiprocessor's shared memory subsystem, evaluate its performance, and discuss problems associated with using commodity workstations and network interconnects as the building blocks of a scalable shared memory multiprocessor. Compared to other ...Avalanche multiprocessor; Shared memory1997
49 Pascucci, ValerioHybrid Computing for HPC Applications2012
50 Nguyen, Hoa Thanh; Nguyen, Thanh Hoang; Freire, JulianaDeepPeep: A Form Search EngineWe present DeepPeep (http://www.deeppeep.org), a new search engine specialized in Web forms. DeepPeep uses a scalable infrastructure for discovering, organizing and analyzing Web forms which serve as entry points to hidden-Web sites. DeepPeep provides an intuitive interface that allows users t...
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