Filters: Collection: "ir_uspace"
| Creator | Title | Description | Subject | Date | ||
|---|---|---|---|---|---|---|
| 326 |
 |
Davis, Alan L. | Mathematical representation for VLSI arrays | This paper introduces a methodology for mapping algorithmic description into a concurrent implementation on silicon. This methodology can help in the solution of important problems using a new technique for the representation of highly parallel networks. This new approach for the representation of c... | VLSI arrays | 1980 |
| 327 |
 |
Henderson, Thomas C. | Multisensor knowledge systems: interpreting 3-D structure | We describe an approach which facilitates and makes explicit the organization of the knowledge necessary to map multisensor system requirements onto an appropriate assembly of algorithms, processors, sensors, and actuators. We have previously introduced the Multisensor Kernel System and Logical Sens... | Multisensors; Knowledge systems; 3-D structure; Logical Sensors | 1987 |
| 328 |
 |
Shirley, Peter S.; Thompson, William B. | Night rendering | The issues of realistically rendering naturally illuminated scenes at night are examined. This requires accurate models for moonlight, night skylight, and starlight. In addition, several issues in tone reproduction are discussed: eliminatiing high frequency information invisible to scotopic (night v... | Night rendering; Low light -- Computer models | 2000 |
| 329 |
 |
Richardson, William F.; Brunvand, Erik L. | The NSR processor prototype | The NSR Non Synchronous RISC processor is a general purpose processor structured as a collection of self timed units that operate concurrently and communicate over bundled data channels in the style of micropipelines?? These units correspond to standard synchronous pipeline stages such as Instr... | Self-timed Systems; Asynchronous systems; Micropipelines; FPGAs; RISC processor | 1992 |
| 330 |
 |
Gopalakrishnan, Ganesh | On the decidability of shared memory consistency verification | We view shared memories as structures which define relations over the set of programs and their executions. An implementation is modeled by a transducer, where the relation it realizes is its language. This approach allows us to cast shared memory verification as language inclusion. We show tha... | Shared memory; Consistency; Verification | 2005-03-15 |
| 331 |
 |
Gopalakrishnan, Ganesh | Performance studies of PV: an On-the-fly model-checker for LTL-X featuring selective caching and partial order reduction | We present an enumerative model-checker PV that uses a new partial order reduction algorithm called Twophase. This algorithm does not use the in-stack check to implement the proviso, making the combination of Twophase with on-the-fly LTL-X model-checking based on nested depth-first search, as well a... | Model-checker; PV; Performance; On-the-fly; Partial order reduction algorithm;' Twophase | 2001 |
| 332 |
 |
Stoller, Leigh B. | PPE interface and functional specification | This document describes the interface and functional specification of a Protocol Processing Engine (PPE) for workstation clusters. The PPE is intended to provide the support necessary to implement low latency protocols requiring only low resource (cpu and bus bandwidth) consumption. | Protocol Processing Engine; PPE; Workstation clusters | 1995 |
| 333 |
 |
Stoller, Leigh B. | PPE-level protocols for carpet clusters | We describe the lowest level of a suite of protocols for workstation cluster multicomputers: the parts implemented in hardware by a Protocol Processing Engine (PPE) and the software level immediately above the PPE. The stated goal of this work is extremely low end-to-end latency communications on in... | Workstation clusters; Protocol Processing Engine; PPE | 1994 |
| 334 |
 |
Gopalakrishnan, Ganesh | Precision on demand: an improvement in probabilistic hashing | In explicit state (enumerative) model checking, state vectors are often represented in a compressed form in order to reduce storage needs, typically employing fingerprints, bithashes, or state signatures. When using this kind of techniques, it could happen that the compressed image of a nonvisite... | Probabilistic hashing; Model checking | 2007 |
| 335 |
 |
Back, Godmar V. | Processes in KaffeOS: lsolation, resource management, and sharing in Java | Single-language runtime systems, in the form of Java virtual machines, are widely deployed platforms for executing untrusted mobile code. These runtimes provide some of the features that operating systems provide: inter-application memory protection and basic system services. They do not. however, p... | KaffeOS; Single-language; Java virtual machines; Mobile code; Runtimes | 2000 |
| 336 |
 |
Keller, Robert M. | Rediflow architecture prospectus | Rediflow is intended as a multi-function (symbolic and numeric) multiprocessor, demonstrating techniques for achieving speedup for Lisp-coded problems through the use of advanced programming concepts, high-speed communication, and dynamic load-distribution, in a manner suitable for scaling to upward... | Rediflow; Multi-function multiprocessors; Lisp-coded problems | 1985 |
| 337 |
 |
Yang, Yue; Gopalakrishnan, Ganesh; Lindstrom, Gary E. | Rigorous concurrency analysis of multithreaded programs | This paper explores the practicality of conducting program analysis for multithreaded software using constraint solv- ing. By precisely defining the underlying memory consis- tency rules in addition to the intra-thread program seman- tics, our approach orders a unique advantage for program ver- ... | Concurrency analysis; Multithreaded programs | 2003 |
| 338 |
 |
Fujimoto, Richard M. | The roll back chip: hardware support for distributed simulation using time warp | Distributed simulation offers an attractive means of meeting the high computational demands of discrete event simulation programs. The Time Warp mechanism has been proposed to ensure correct sequencing of events in distributed simulation programs without blocking processes unnecessarily. However, th... | Roll back chip; Distributed simulation; Discrete event; Simulation programs; Time Warp mechanism | 1987 |
| 339 |
 |
Mahi, Robert | Scheduling multiprogammed computer systems: an analytical approach | In a multiprogrammed computer system, several jobs are using the facilities of the system at the same time. However, a given facility (or resource) is generally only allocated to one user at a time- But, while working, jobs generate requests for some facilities and liberate other facilities; thus, c... | Multiprogrammed computer system | 1970 |
| 340 |
 |
Lindstrom, Gary E. | Toward function-based distributed database systems | We discuss the suitability of a function-based (or "applicative") approach to the construction of distributed database systems. Certain aspects of applicative systems are immediatley appealing for this purpose (e.g. data oriented toward conceptual objects rather than toward particular representation... | Function-based; distributed database systems; applicative | 1982 |
| 341 |
 |
Organick, Elliott I.; Lindstrom, Gary E. | Transforming an Ada program unit to silicon and verifying its behavior in an Ada environment: a first experiment | Microelectronics technology has advanced so rapidly and been so successful that we are new having to build large systems with a multitude of diverse, interacting components. Some components of these systems exhibit distinct architectures and may, in fact, be implemented following different choices o... | Transformation; Ada program units; Silicon | 1983 |
| 342 |
 |
Grodstein, Joel | User's manual for the sisyphus simulation environment | This report describes how to create and simulate a design with Sisyphus. Inasmuch as Sisyphus is written in Symbolics-Lisp, some familiarity with both Lisp and with Symbolics computers is presumed. In addition, the concepts presented here presume an acquaintance with [3]. First, a disclaimer ? this... | Sisyphus; Simulation environment; Symbolics-Lisp; Symbolics computers | 1986 |
| 343 |
 |
Hibler, Michael J. | Using annotated interface definitions to optimize RPC | In RPC-based communication, it is useful to distinguish the RPC interface, which is the "network contract" between the client and the server, from the presentation, which is the "programmer's contract" between the RPC stubs and the code that calls or is called by them. Presentation is usually a fixe... | annotated interface definitions; RPC-based communication | 1995 |
| 344 |
 |
Kessler, Robert R. | Using utilization profiles in allocation and partitioning for multiprocessor systems | The problems of multiprocessor partitioning and program allocation are interdependent and critical to the performance of multiprocessor systems. Minimizing resource partitions for parallel programs on partitionable multiprocessors facilitates greater processor utilization and throughput. The proces... | utilization profiles; multiprocessor partitioning; program allocation | 1992 |
| 345 |
 |
Kessler, Robert R. | A communication-ordered task graph allocation algorithm | The inherently asynchronous nature of the data flow computation model allows the exploitation of maximum parallelism in program execution. While this computational model holds great promise, several problems must be solved in order to achieve a high degree of program performance. The allocation and ... | Task graph allocation algorithm | 1992 |
| 346 |
 |
Gopalakrishnan, Ganesh | A partial order reduction algorithm without the Proviso | This paper presents a partial order reduction algorithm, called Two phase, that preserves stutter free LTL properties. Two phase dramatically reduces the number of states visited compared to previous partial order reduction algorithms on most practical protocols. The reason can be traced to a step o... | Order reduction algorithm; Proviso step | 1998 |
| 347 |
 |
McDirmid, Sean; Hsieh, Wilson C. | A path-precise analysis for property synthesis | Recent systems such as SLAM, Metal, and ESP help programmers by automating reasoning about the correctness of temporal program properties. This paper presents a technique called property synthesis, which can be viewed as the inverse of property checking. We show that the code for some program pro... | Property synthesis; Property codes | 2003-12-01 |
| 348 |
 |
Henderson, Thomas C. | A study of Pierce's group generator | Pierce describes an approach to map learning with uninterpreted sensors and effectors. As part of that, he describes a sensor grouping generator operator that attempts to arrange similar sensors into groups. Here we review that work and place it in a more strenuous statistical validation framewor... | Pierce's group; Map learning; Sensor grouping generator | 2010 |
| 349 |
 |
Keller, Robert M.; Lindstrom, Gary E. | An architecture for a loosely-coupled parallel processor | An architecture for a large (e. g. 1000 processor) parallel computer is presented. The processors are loosely-coupled, in the sense that communication among them is fully asynchronous, and each processor is generally not unduly delayed by any immediate need for specific data values. The network supp... | Loosely-coupled; Parallel processors | 1978 |
| 350 |
 |
Bruderlin, Beat | An axiomatic approach for solving geometric problems symbolically | This paper describes a new approach for solving geometric constraint problems and problems in geometry theorem proving. We developed a rewrite-rule mechanism operating on geometric predicates. Termination and completeness of the problem solving algorithm can be obtained through well foundedness and ... | Geometric constraint problems; Geometry theorem proving; Knuth-Bendix completion algorithm | 1990 |