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CreatorTitleDescriptionSubjectDate
1 Stevens, KennethAn A-FPGA architecture for relative timing based asynchronous designsThis paper presents an asynchronous FPGA architecture that is capable of implementing relative timing based asynchronous designs. The architecture uses the Xilinx 7-Series architecture as a starting point and proposes modifications that would make it asynchronous design capable while keeping it full...2014-01-01
2 Myers, Chris J.An asynchronous implementations of the MAXLIST algorithmABSTRACT We present an efficient asynchronous VLSI architecture for calculating running maximum or minimum values over a sliding window. Running maximums or minimums are very useful for many signal and image processing tasks. Our architecture performs the calculation using the MAXLIST algorithm. In...1997
3 Lindstrom, Gary E.The design of object-oriented meta-architectures for programming languagesThis paper is a survey of the design of four object-oriented meta-level architectures for programming languages. We present overviews and compare the salient features of the meta-architectures of Smalltalk, Common Lisp Object System (CLOS), a Scheme Compiler, and Etyma, our framework for modular sy...Meta-level architectures; Design1994
4 Stevens, KennethA mathematical approach to a low power FFT architectureArchitecture and circuit design are the two most effective means of reducing power in CMOS VLSI. Mathematical manipulations have been applied to create a power efficient architecture of an FFT. This architecture has been implemented in asynchronous circuit technology that achieves significant powe...1998
5 Normann, Richard A.; Johansson,Torbjorn; Abbasi, Masoud; Huber, Robert J.Three-dimensional architecture for a parallel processing photosensing arrayA three-dimensional architecture for a photosensing array has been developed. This silicon based architecture consists of a 10 x 10 array of photosensors with 80 microns diameter, through chip interconnects to the back side of a 500 microns thick silicon wafer. Each photosensor consists of a 300 x 3...Retina; Optics; Silicon; Photosensing1992
6 Gu, JunAn optimal, parallel discrete relaxation algorithm and architecture (Revised January 1988 and August 1989)A variety of problems in artificial intelligence, operations research, symbolic logic, pattern recognition and computer vision, and robot manipulation are special cases of the Consistent Labeling Problem (CLP). The Discrete Relaxation Algorithm (DRA) is an efficient computational technique to enfor...Consistent Labeling Problem; CLP; Discrete Relaxation Algorithm; DRA1988
7 Kuramkote, Ravindra; Carter, JohnExploring the value of supporting multiple DSM protocols in Hardware DSM ControllersThe performance of a hardware distributed shared memory (DSM) system is largely dependent on its architect's ability to reduce the number of remote memory misses that occur. Previous attempts to solve this problem have included measures such as supporting both the CC-NUMA and S-COMA architectures is...DSM; Controllers1999
8 Stevens, KennethMultirate as a hardware paradigmArchitecture and circuit design are the two most effective means of reducing power in CMOS VLSI. Mathematical manipulations, based on applying ideas from multirate signal processing have been applied to create high performance, low power architectures. To illustrate this approach, two case studies...1999
9 Brunvand, Erik L.; Smith, Kent F.Self-timed design in GaAs - case study of a high-speed parallel multiplierAbstract-The problems with synchronous designs at high clock frequencies have been well documented. This makes an asynchronous approach attractive for high speed technologies like GaAs. We investigate the issues involved by describing the design of a parallel multiplier that can be part of a floati...1996
10 Jacobson, HansDesign and validation of a simultaneous multi-threaded DLX processorModern day computer systems rely on two forms of parallelism to achieve high performance, parallelism between individual instructions of a program (ILP) and parallelism between individual threads (TLP). Superscalar processors exploit ILP by issuing several instructions per clock, and multiprocessors...DLX processor; Validation1999
11 Stevens, KennethTotal ionizing dose characterization of a commercially fabricated asynchronous FFT for space applicationsThe total ionizing dose characterization of the radiation-hardened implementation of a novel architecture for high-performance, energy efficiency FFT engines is presented. Simulations and test chip measurement results indicate that a radiation-tolerant 1024-point FFT based on this architecture will...2000
12 Michell, NickOn the potential of asynchronous pipelined processorsAn asynchronous version of the pipelined R3000 and DLX processors, the A3000, is being designed. Simulation was employed t o investigate the potential speed-up obtainable due t o the asynchronous operation. Preliminary results show up to a 64% improvement in performance.Pipelined processors; Pipelined R3000; DLX processors; A30001990
13 Davis, A.L.The architecture of DDMl: a recursively structured data driven machineAn architecture for a highly modular, recursively structured class of machines is presented. DDMl is an instance of such a machine structure, and is capable of executing machine language programs which are data driven (data flow) nets. These nets may represent arbitrary amounts of concurrency as wel...DDMl; machine structure; machine language programs1977
14 Carter, John B.Design alternatives for shared memory multiprocessorsIn this paper. we consider the design alternatives available for building the next generation DSM machine (e.g., the choice of memory architecture, network technology, and amount and location of per-node remote data cache). To investigate this design space, we have simulated six applications on a wi...Shared memory multiprocessors1998
15 Balasubramonian, RajeevExploring the design space for 3D clustered architectures3D die-stacked chips are emerging as intriguing prospects for the future because of their ability to reduce on-chip wire delays and power consumption. However, they will likely cause an increase in chip operating temperature, which is already a major bottleneck in modern microprocessor design. We...2006
16 Sudan, KshitijUnderstanding the behavior of Pthread applications on non-uniform cache architecturesWhy is it important? As number of cores in a processor scale up, caches would become banked Keeps individual look-up time small. Allows parallel accesses by different cores. Present shared programming model assumes a flat memory. Unaware application can have sub-optimal performance Conclusion ...Computer architecture, compiler analysis, NUCA caches2011-10-08
17 Scheer, BrendaUrban morphology and urban designThere has recently been a flurry of discussion in this journal about the relationship between urban morphological research and practice (Hall, 2008; Samuels, 2008; Whitehand, 2007). As a practising architect and planner, I have frequently applied the concepts of typology and morphology in my desi...Urban morphology; Urban design2008
18 Riloff, Ellen M.Recognizing and organizing opinions expressed in the world pressTomorrow's question answering systems will need to have the ability to process information about beliefs, opinions, and evaluations-the perspective of an agent. Answers to many simple factual questions-even yes/no questions-are affected by the perspective of the information source. For example...Opinions; Opinion recognition; World press; MPQA project; Multiple perspectives2003
19 Parker, Steven G.Survey of the Itanium architecture from a programmer's perspectiveThe Itanium family of processors represents Intel;s foray into the world of Explicitly Parallel Instruction Computing and 64-bit system design. This survey contains an introduction to the Itanium architecture and instruction set, as well as some of the available implementations. Taking a programmer'...Itanium; Instruction sets2003
20 Brunvand, Erik L.Fred: an architecture for a self-timed decoupled computerDecoupled computer architectures provide an effective means of exploiting instruction level parallelism. Selftimed micropipeline systems are inherently decoupled due to the elastic nature of the basic FIFO structure, and may be ideally suited for constructing decoupled computer architectures. Fred ...1996
21 DuVall, Scott L.Creation of an open source master person index from proprietary code: the open source "care data exchange" projectFrom 1998 to 2004 the ""Care Data Exchange"" (CDE) software was developed as a proprietary product by CareScience for the California HealthCare Foundation (CHCF). In 2005 CHCF asked Forrester Research to study the feasibility of releasing the CDE software assets under a free, open source license. Th...Care Data Exchange; CDE; Proprietary code; Forrester report; Trapeze Interactive Poster2009
22 Carter, John B.; Davis, Al; Kuramkote, Ravindra; Stoller, Leigh B.Avalanche: A communication and memory architecture for scalable parallel computingAs the gap between processor and memory speeds widens?? system designers will inevitably incorpo rate increasingly deep memory hierarchies to maintain the balance between processor and memory system performance At the same time?? most communication subsystems are permitted access only to main m...Avalanche; Communication architecture; Memory architecture1995
23 Seyedhosseini Tarzjani, Seyed MojtabaNeural Circuit Reconstruction using electron microscopy2012
24 Richardson, William F.Fred: an architecture for a self-timed decoupled computerDecoupled computer architectures provide an effective means of exploiting instruction level parallelism. Self-timed micropipeline systems are inherently decoupled due to the elastic nature of the basic FIFO structure, and may be ideally suited for constructing decoupled computer architectures. Fred ...Decoupled computer; Fred1995
25 Henderson, Thomas C.An O(n) time discrete relaxation architecture for real-time processing of the consistent labeling problemDiscrete relaxation techniques have proven useful in solving a wide range of problems in digital signal and digital image processing, artificial intelligence, operations research, and machine vision. Much work has been devoted to finding efficient hardware architectures. This paper shows that a conv...Discrete relaxation techniques1986
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