UScholar Works
 
Filters: Collection: "ir_uspace" Subject: "Verification"
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CreatorTitleDescriptionSubjectDate
1 Gopalakrishnan, GaneshVerifying a virtual component interface-based PCI bus wrapper using an LSC-based specificationBecause of the high stakes involved in integrating externally developed intellectual property (IP) cores used in System on Chip (SOC) designs, methods and tool support for quick, easy, decisive standard compliance verification must be developed. Such methods and tools include formal standard spec...System on Chip; SOC; Verification; PCI bus wrapper; LSC2002-01-22
2 Gopalakrishnan, Ganesh; Kirby, Robert Michael IIVerification of MPI programs using SpinVerification of distributed systems is a complex yet important process. Concurrent systems are vulnerable to problems such as deadlock, starvation, and race conditions. Parallel programs written using the MPI (Message Passing Interface) Standard are no exception. Spin can be used to formally ver...MPI programs; Verification; distributed systems; Message Passing Interface; Spin2004
3 Gopalakrishnan, GaneshDesign and verification of the rollback chip using HOP: a case study of formal methods applied to hardware designThe use of formal methods in hardware design improves the quality of designs in many ways: it promotes better understanding of the design; it permits systematic design refinement through the discovery of invariants; and it allows design verification (informal or formal). In this paper we illustrate ...Rollback chip; Verification; HOP; Hardware design; RBC1990
4 Gopalakrishnan, GaneshThe 'Test model-checking' approach to the verification of formal memory models of multiprocessorsWe offer a solution to the problem of verifying formal memory models of processors by combining the strengths of model-checking and a formal testing procedure for parallel machines. We characterize the formal basis for abstracting the tests into test automata and associated memory rule safety proper...Test Model-checking; Formal memory; Verification1998
5 Gopalakrishnan, GaneshVerifying a virtual component interface-based PCI bus wrapper with FormalCheckThe Virtual Sockets Interface Alliance (VSIA) recently released the Virtual Component Interface (VCI) Standard. This paper reports recent experiences in formally verifying a few properties of a VCI-compliant PCI 2.1 bus wrapper model in the formal verification tool, FormalCheck. Though we chose t...Virtual Sockets Interface Alliance; VSIA; Virtual Component Interface Standard; VCI; Verification; PCI bus wrapper; FormalCheck2001-06-14
6 Gopalakrishnan, GaneshA general compositional approach to verifying hierarchical cache coherence protocolsModern chip multiprocessor (CMP) cache coherence protocols are extremely complex and error prone to design. Modern symbolic methods are unable to provide much leverage for this class of examples. In [1], we presented a method to verify hierarchical and inclusive versions of these protocols using ...Hierarchical cache coherence protocols; Verification2006-11-26
7 Sikorski, ChristopherThe method of generated solutions for numerical verification of ICE codeMethod of Manufactured Solutions (MMS) is a widely used technique to verify convergence and possible coding errors in numerical algorithms. This method involves designing analytical solutions satisfying the governing equations that are solved by the numerical algorithm. The solutions investigated...Method of Manufactured Solutions; MMS; Convergence; Verification; numerical Algorithms; ICE code; Numerical verification2007
8 Panangaden, PrakashVerification of systolic arrays: a stream functional approachWe illustrate that the verification of systolic architectures can be carried out using techniques developed in the context of verification of programs. This is achieved by a decomposition of the original problem into separately proving the correctness of the data representation and of the individual...Verification; systolic arrays; stream function1985
9 Gopalakrishnan, GaneshTowards a verification technique for large synchronous circuitsWe present a symbolic simulation based verification approach which can be applied to large synchronous circuits. A new technique to encode the state and input constraints as parametric Boolean expressions over the state and input variables is used to make our symbolic simulation based verification...Verification; symbolic simulation1992
10 Gopalakrishnan, GaneshVerification of regular arrays by symbolic simulationMany algorithms have an efficient hardware formulation as a regular array of cells, which can be implemented in VLSI as regular circuit structures. Bit-sliced microprocessors, pattern matching circuits, associative cache memories, Hue-grain systolic arrays, and embedded memory-with-logic structure...Verification; regular arrays; symbolic simulation1991
11 Gopalakrishnan, GaneshEfficient symbolic simulation based verification using the parametric form of boolean expressions (rev.)We present several new techniques to make symbolic simulation based verification efficient. These techniques hinge on the use of the parametric form of a boolean expression (e.g. the parametric form for the boolean expression XQ V -<xi is the equivalent expression 3a b . (XQ = a V 6) A (xi = b), whe...Symbolic simulation; Verification1991
12 Gopalakrishnan, GaneshExplicit-enumeration based verification made memory-efficientWe investigate techniques for reducing the memory requirements of a model checking tool employing explicit enumeration. Two techniques are studied in depth: (1) exploiting symmetries in the model, and (2) exploiting sequential regions in the model. The first technique resulted in a significant reduc...Verification; Model checking tool; Memory-efficient1995
13 Sikorski, ChristopherMethod of generated solutions as a numerical verification tool for ice codeMethod of Manufactured solutions is a well-known method used to verify numerical algorithms. It is used to estimate convergence and order of accuracy of the algorithms. The method involves design of analytical solutions to the set of equations solved by the algorithm and generation of the forcing fu...Validation; Verification; Method of Generated Solutions; Finite volume solver; ICE code2007
14 Gopalakrishnan, GaneshOn the decidability of shared memory consistency verificationWe view shared memories as structures which define relations over the set of programs and their executions. An implementation is modeled by a transducer, where the relation it realizes is its language. This approach allows us to cast shared memory verification as language inclusion. We show tha...Shared memory; Consistency; Verification2005-03-15
15 Gopalakrishnan, GaneshAn interface aware guided search method for error-trace justification in large protocolsMany complex concurrent protocols that cannot be formally verified due to state explosion can often be formally verified by initially creating a collection of abstractions (overapproximations), and subsequently refining the overapproximated protocol in response to spurious counterexample traces. ...Concurrent protocols; Verification; Error-trace justification2008
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