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| Creator | Title | Description | Subject | Date | ||
|---|---|---|---|---|---|---|
| 1 |
 | Gopalakrishnan, Ganesh | High level optimizations in compiling process descriptions to asynchronous circuits | Asynchronous/'Self-Timed designs are beginning to attract attention as promising means of dealing with the complexity of modern VLSI technology. In this paper, we present our views on why asynchronous systems matter. We then present details of our high level synthesis tool SHILPA that can automatic... | Self-timed; VLSI | 1992 |
| 2 |
 | Brunvand, Erik L. | Reduced latency self-timed FIFO circuits | Self-timed flow-through FIFOs are constructed easily using only a single C-element as control for each stage of the FIFO. Throughput can be very high in FIFOs of this type because new data can be sent to the FIFO after communicating locally with only the first element of the FIFO. Therefore the thro... | FIFO circuits; Self-timed; Flow-through; Reduced latency | 1994 |
| 3 |
 | Brunvand, Erik L. | A comparison of modular self-timed design styles | State-machine sequencing methods in modular 2-phase and 4-phase asynchronous handshake control are compared. Design styles are discussed, and the sequencers are tested against each other using a medium-scale minicomputer test design implemented in FPGAs. Seven 4-phase sequencers are tested. In these... | Self-timed; State-machine sequencing; Asynchronous handshake control | 1995 |
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