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 | Balasubramonian, Rajeev | Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy | Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postulate a 3D chip design that stacks SRAM and DRAM upon processing cores and employs OS-based page coloring to minimize hori... | Multi-core processors; Cache and memory hierarchy; Non-uniform cache architecture (NUCA); Page coloring; On-chip networks; SRAM/DRAM cache reconfiguration | 2009-02 |
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