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| Creator | Title | Description | Subject | Date | ||
|---|---|---|---|---|---|---|
| 1 |
 | Balasubramonian, Rajeev | Microarchitectural wire management for performance and power in partitioned architectures | Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low power. In such architectures, inter-partition communication over global wires has a significant impact on overall proc... | Microarchitecture; Partitioned architectures; Heterogeneous interconnects; Cache access | 2005 |
| 2 |
 | Balasubramonian, Rajeev | Power efficient resource scaling in partitioned architectures through dynamic heterogeneity | The ever increasing demand for high clock speeds and the desire to exploit abundant transistor budgets have resulted in alarming increases in processor power dissipation. Partitioned (or clustered) architectures have been proposed in recent years to address scalability concerns in future billion-tr... | Partitioned architectures; Clustered architectures; Energy × Delay2, Temperature; Dynamic frequency scaling; Thermal emergency | 2006 |
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