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| Creator | Title | Description | Subject | Date | ||
|---|---|---|---|---|---|---|
| 1 |
 | Balasubramonian, Rajeev | Dynamically allocating processor resources between nearby and distant ILP | Modern superscalar processors use wide instruction issue widths and out-of-order execution in order to increase instruction-level parallelism (ILP). Because instructions must be committed in order so as to guarantee precise exceptions, increasing ILP implies increasing the sizes of structures s... | Instruction-level parallelism; Microarchitecture; Primary thread; Future thread; Instruction reuse buffer | 2001 |
| 2 |
 | Balasubramonian, Rajeev | Dynamically managing the communication-parallelism trade-off in future clustered processors | Clustered microarchitectures are an attractive alternative to large monolithic superscalar designs due to their potential for higher clock rates in the face of increasingly wire-delay-constrained process technologies. As increasing transistor counts allow an increase in the number of clusters, th... | Clustered architectures; Microarchitecture; Decentralized cache; Interconnects | 2003 |
| 3 |
 | Balasubramonian, Rajeev | Dynamically tunable memory hierarchy | The widespread use of repeaters in long wires creates the possibility of dynamically sizing regular on-chip structures. We present a tunable cache and translation lookaside buffer (TLB) hierarchy that leverages repeater insertion to dynamically trade off size for speed and power consumption on a per... | Microarchitecture; High performance microprocessors; Reconfigurable architectures; Energy and performance of on-chip caches; Translation lookaside buffer (TLB); Tunable cache | 2003-10 |
| 4 |
 | Balasubramonian, Rajeev | Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling | As clock frequency increases and feature size decreases, clock distribution and wire delays present a growing challenge to the designers of singly-clocked, globally synchronous systems. We describe an alternative approach, which we call a Multiple Clock Domain (MCD) processor in which the chip is d... | Multiple clock domains; Synchronization; Microarchitecture | 2002 |
| 5 |
 | Balasubramonian, Rajeev | Integrating adaptive on-chip storage structures for reduced dynamic power | Energy efficiency in microarchitectures has become a necessity. Significant dynamic energy savings can be realized for adaptive storage structures such as caches, issue queues, and register files by disabling unnecessary storage resources. Prior studies have analyzed individual structures and their... | Microarchitecture | 2002 |
| 6 |
 | Balasubramonian, Rajeev | Leveraging wire properties at the microarchitecture level | In future microprocessors, communication will emerge as a major bottleneck. The authors advocate composing future interconnects of some wires that minimize latency, some that maximize bandwidth, and some that minimize power. A microarchitecture aware of these wire characteristics can steer on-chip ... | Microarchitecture; Interconnects; Cache coherence | 2006-11 |
| 7 |
 | Balasubramonian, Rajeev | Microarchitectural wire management for performance and power in partitioned architectures | Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low power. In such architectures, inter-partition communication over global wires has a significant impact on overall proc... | Microarchitecture; Partitioned architectures; Heterogeneous interconnects; Cache access | 2005 |
| 8 |
 | Balasubramonian, Rajeev | Reducing the complexity of the register file in dynamic superscalar processors | Dynamic superscalar processors execute multiple instructions out-of-order by looking for independent operations within a large window. The number of physical registers within the processor has a direct impact on the size of this window as most in-flight instructions require a new physical register a... | Dynamic superscalar processors; Register file; Instruction-level parallelism; Microarchitecture; Reorder buffer | 2001 |
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