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576 - 600 of 1,978
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CreatorTitleDescriptionSubjectDate
576 Evans, JohnDPOS programming manualThis manual describes the basic concepts of the DPOS Metalanguage and the programming language DPOS Scheme.DPOS; Programming manual1990
577 Kessler, Robert R.DPOS: A metalanguage and programming environment for parallel processorsThe complexity and diversity of parallel programming languages and computer architectures hinders programmers in developing programs and greatly limits program portability. All MIMD parallel programming systems, however, address common requirements for process creation, process management, and inte...DPOS; MIMD parallel programming1990
578 Lepreau, JayDRAFT: work in progress - - - comments solicited evolving Mach 3.0 to use migrating threadsLike most operating systems, Mach 3.0 views threads as statically associated with a single task. An alternative model is that of migrating threads, in which a single thread abstraction moves between tasks with the logical flow of control, and "server" code is passively executed. We have compatibly r...DRAFT1993
579 Eckhoff, David W.Drought happens: get used to it! Will technology help us to survive?Drought is not the most popular subject in the world. Actually, as opposed to death, I think there are some bright spots in the drought mitigation future. I will review some of these in this lecture, but I'm also going to discuss some of the downsides of drought, because you can't have one without t...Wastewater reclamation; Tiered water rates2002-09-10
580 Gesteland, Raymond F.; Atkins, John F.; Ingram, Jennifer A.; Kelly, Paul J.; Grentzmann, GuidoDual-luciferase reporter system for studying recoding signalsA new reporter system has been developed for measuring translation coupling efficiency of recoding mechanisms such as frameshifting or readthrough. A recoding test sequence is cloned in between the renilla and firefly luciferase reporter genes and the two luciferase activities are subsequently measu...Amino Acid Sequence; Genes, Reporter; HIV; Antizyme; Translation1998
581 Stringfellow, Gerald B.; Zhu, Jing Yi; Liu, FengDual-surfactant effect to enhance p-type doping in III-V semiconductor thin filmsSurfactant effects are usually achieved by the addition of a single surface element. We demonstrate by first-principles calculations a dual-surfactant effect of Sb and H on enhancing Zn doping in organometallic vapor phase epitaxially grown GaP thin films. The combined effects of Sb and H lower sig...Surfactants; p-type doping2008-11
582 Regehr, JohnDynamic CPU management for real-time, middleware-based systemsMany real-world distributed, real-time, embedded (DRE) systems, such as multi-agent military applications, are built using commercially available operating systems, middleware, and collections of pre-existing software. The complexity of these systems makes it difficult to ensure that they maintain h...2004-01-01
583 Eide, Eric Norman; Regehr, John; Lepreau, JayDynamic CPU management for real-time, middleware-based systemsMany real-world distributed, real-time, embedded (DRE) systems, such as multi-agent military applications, are built using commercially available operating systems, middleware, and collections of pre-existing software. The complexity of these systems makes it difficult to ensure that they maintai...CPU management2004-01-30
584 Stevens, KennethDynamic gates with hysteresis and configurable noise toleranceDynamic logic can provide significant performance and power benefit compared to implementations using static gates. Unfortunately dynamic gates have traditionally suffered from low noise margins, which limits their reliability. A new logic family, called complementary dynamic logic (CDL), is prese...2007
585 Balasubramonian, RajeevDynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large cachesIn future multi-cores, large amounts of delay and power will be spent accessing data in large L2/L3 caches. It has been recently shown that OS-based page coloring allows a non-uniform cache architecture (NUCA) to provide low latencies and not be hindered by complex data search mechanisms. In this ...Page coloring; Shadow-memory addresses; Cache capacity allocation; Data/page migration; Last level caches; Non-uniform cache architectures (NUCA)2009-02
586 Balasubramonian, RajeevDynamic memory hierarchy performance optimizationAlthough microprocessor performance continues to increase at a rapid pace, the growing processor-memory speed gap threatens to limit future performance gains. In this paper, we propose a novel configurable cache and TLB as an alternative to conventional two-level hierarchies. This organization le...Microprocessor performance; Processor-memory speed gap2000
587 Zhou, XuesongDynamic origin-destination demand estimation using automatic vehicle identification dataAbstract-This paper proposes a dynamic origin-destination (OD) estimation method to extract valuable point-to-point splitfraction information from automatic vehicle identification (AVI) counts without estimating market-penetration rates and identification rates of AVI tags. A nonlinear ordinary leas...2006
588 Orr, Douglas B.; Mecklenburg, Robert; Hoogenboom, Peter J.; Lepreau, JayDynamic program monitoring and transformation using the OMOS object serverIn traditional monolithic operating systems the con?? straints of working within the kernel have limited the sophistication of the schemes used to manage exe?? cutable program images By implementing an exe?? cutable image loader as a persistent user??space pro?? gram we can extend system prog...Program monitoring; OMOS object server1992
589 Orr, Douglas B.Dynamic program monitoring and transformation using the OMOS object serverIn traditional monolithic operating systems the constraints of working within the kernel have limited the sophistication of the schemes used to manage executable program images. By implementing an executable image loader as a persistent user-space program, we can extend system program loading capabi...Program monitoring; Object/Meta-Object Server; OMOS1992
590 Gopalakrishnan, GaneshDynamic reordering of high latency transactions in time-warp simulation using a modified micropipelineTime warp based simulation of discrete-event systems is an efficient way to overcome the synchronization overhead during distributed simulation. As computations may proceed beyond synchronization barriers in time warp, multiple checkpoints of state need to be maintained to be able to rollback inva...Asynchronous design; Micropipelines; Dynamic instruction reordering; Time warp simulations1992
591 Rashid, Khalid; Powell, KodyDynamic simulation, control, and design of a novel solar thermal hybrid power plantSolar power is among the promising technologies leading towards cleaner fuel. However, there are still technological challenges regarding the reliability of power generation due to its intermittency. This work demonstrates the synergies that exist in integrated hybrid systems, where a dispatchable f...Solar energy--Research; Solar thermal energy--Research; Solar power plants--Research2017
592 Bargteil, Adam WadeDynamic spritesTraditional methods for creating dynamic objects and characters from static drawings involve careful tweaking of animation curves and/or simulation parameters. Sprite sheets offer a more drawing-centric solution, but they do not encode timing information or the logic that determines how objects shou...2014-01-01
593 Bargteil, Adam WadeDynamic spritesTraditional methods for creating dynamic objects and characters from static drawings involve careful tweaking of animation curves and/or simulation parameters. Sprite sheets offer a more drawing-centric solution, but they do not encode timing information or the logic that determines how objects shou...2013-01-01
594 Balasubramonian, RajeevDynamically allocating processor resources between nearby and distant ILPModern superscalar processors use wide instruction issue widths and out-of-order execution in order to increase instruction-level parallelism (ILP). Because instructions must be committed in order so as to guarantee precise exceptions, increasing ILP implies increasing the sizes of structures s...Instruction-level parallelism; Microarchitecture; Primary thread; Future thread; Instruction reuse buffer2001
595 Balasubramonian, RajeevDynamically managing the communication-parallelism trade-off in future clustered processorsClustered microarchitectures are an attractive alternative to large monolithic superscalar designs due to their potential for higher clock rates in the face of increasingly wire-delay-constrained process technologies. As increasing transistor counts allow an increase in the number of clusters, th...Clustered architectures; Microarchitecture; Decentralized cache; Interconnects2003
596 Balasubramonian, RajeevDynamically tunable memory hierarchyThe widespread use of repeaters in long wires creates the possibility of dynamically sizing regular on-chip structures. We present a tunable cache and translation lookaside buffer (TLB) hierarchy that leverages repeater insertion to dynamically trade off size for speed and power consumption on a per...Microarchitecture; High performance microprocessors; Reconfigurable architectures; Energy and performance of on-chip caches; Translation lookaside buffer (TLB); Tunable cache2003-10
597 Balasubramonian, RajeevDynamically tuning processor resources with adaptive processingUsing adaptive processing to dynamically tune major microprocessor resources, developers can achieve greater energy efficiency with reasonable hardware and software overhead while avoiding undue performance loss.Adaptive processing; Energy efficiency; DRI-cache2003-12
598 Tasdizen, TolgaEdge enhanced spatio-temporal constrained reconstruction of undersampled dynamic contrast enhanced radial MRIThere are many applications in MRI where it is desirable to have high spatial and high temporal resolution. This can be achieved by undersampling of k-space and requires special techniques for reconstruction. Even if undersampling artifacts are removed, sharpness of the edges can be a problem. We pr...2010
599 Regehr, JohnEdicts: implementing features with flexible binding timesIn a software product line, the binding time of a feature is the time at which one decides to include or exclude a feature from a product. Typical binding site implementations are intended to support a single binding time only, e.g., compile time or run time. Sometimes, however, a product line must...2008-01-01
600 Brunvand, Erik L.Editorial asynchronous architectureAsynchronous design is enjoying a worldwide resurgence of interest following several decades in obscurity. Many of the early computers employed asynchronous design techniques, but since the mid 1970s almost all digital design has been based around the use of a central clock. The clock simplifies mos...1996-01-01
576 - 600 of 1,978