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CreatorTitleDescriptionSubjectDate
1 Stevens, KennethDynamic gates with hysteresis and configurable noise toleranceDynamic logic can provide significant performance and power benefit compared to implementations using static gates. Unfortunately dynamic gates have traditionally suffered from low noise margins, which limits their reliability. A new logic family, called complementary dynamic logic (CDL), is prese...2007
2 Harrison, Reid R.; Charles, Cameron TownleyFloating gate common mode feedback circuit for low noise amplifiersMost low noise amplifier designs focus on eliminating sources of noise that are intrinsic 1.0 the amplifier (thermal noise, Ilfnoise). As integrated (circuit design moves increasingly towards mixed signal implementations, the design of low-noise malog amplifiers must be re-evaluated to consider th...Floating gate; Common mode feedback circuit; Low noise amplifiers2003-01-01
3 Stevens, KennethAutomatic addition of reset in asynchronous sequential control circuitsAsynchronous finite state machines (AFSMs) usually require initialization to place them in a desired starting state. This normally occurs by toggling a reset signal upon power-up. This paper presents an algorithm to automatically generate power-up reset circuitry thus adding reset to an AFSM after t...2014-01-01
4 Harrison, Reid R.Floating-gate PFET-based CMOS programmable analog memory cell arrayThe complexity of analog VLSI systems is often limited by the number of pins on a chip rather than by the die area. Currently, many analog parameters and biases are stored off chip. Moving parameter storage on chip could save pins and allow us to create complex programmable analog systems. In this ...2000-01-01
5 Harrison, Reid R.Wide-linear-range subthreshold CMOS transconductor employing the back-gate effectWe present a CMOS circuit that utilizes the back-gate effect to extend the linear range of a subthreshold MOS transconductor. Previous designs of wide-linear-range transconductors using bipolar transistors employed multiple differential pairs with input offset voltages used to shift the individ...2002-01-01
6 Myers, Chris J.Technology mapping of timed circuitsAbstract This paper presents an automated procedure for the technology mapping of timed circuits to practical gate libraries. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the specification which is used throughout the design process to optimi...1995
7 Harrison, Reid R.CMOS programmable analog memory-cell array using floating-gate circuitsThe complexity of analog VLSI systems is often limited by the number of pins on a chip rather than by the die area. Currently, many analog parameters and biases are stored off-chip. Moving parameter storage on-chip could save pins and allow us to create complex programmable analog systems. In this ...Computer chips; VLSI; Computer memory; Potentiometers; CMOS circuits; Floating gate circuit2001-01
8 Harrison, Reid R.Floating gate current mirror for gain correction in CMOS translinear circuitsThe exponential behavior of MOSFETs in subthreshold operation has recently been exploited to build CMOS translinear circuits such as multipliers and log-domain filters. A major obstacle in developing a practical CMOS implementation is the variation in threshold voltage between devices. In transline...1999-01-01
9 Stevens, KennethFsimac: a fault simulator for asynchronous sequential circuitsAt very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper presents Fsimac, a gate-level fault simulator for stuck-at and gate-delay faults in asynchronous sequential circuits. Fsimac...2000
10 Michell, NickPPL 1.2mu gallium arsenide cell setThe purpose of this note is to describe the 1.2/i gallium arsenide PPL cell set - not only what is included, but design decisions made along the way. The first section is an overview of the Umitations imposed by the use of gallium arsenide technology, the next section describes the trade-offs in des...Gallium arsenide cells; PPL cell set1993
11 Stevens, KennethAlgorithms for MIS vector generation and pruningIgnoring the effect of simultaneous switching for logic gates causes silicon failures for high performance microprocessor designs. The main reason to omit this effect is the run time penalty and potential over-conservatism. Run times are directly proportional to the vector sizes. Efficient algorithm...2006
12 Myers, Chris J.Verification of delayed-reset domino circuits using ATACSThis paper discusses the application of the timing analysis tool ATACS to the high performance, self-resetting and delayed-reset domino circuits being designed at IBM's Austin Research Laboratory. The tool, which was originally developed to deal with asynchronous circuits, is well suited to the se...1999
13 Myers, Chris J.Design of a genetic muller C-elementSynthetic biology uses engineering principles to design circuits out of genetic materials that are inserted into bacteria to perform various tasks. While synthetic combinational Boolean logic gates have been constructed, there are many open issues in the design of sequential logic gates. One such g...2007
14 Carter, Tony M.Path-programmable logicPath-Programmable Logic (PPL) is a structured IC design methodology under development at the University of Utah. PPL employs a sea-of-wires approach to design. In PPL, design is done entirely using cells for both functionality and interconnect. PPL cells may have modifiers that change either their ...Path-Programmable Logic; PPL1989
15 Jacobson, HansRealizing burstmode circuits via STG speed independent synthesisThis report discusses the similarities and differences of STG and Burstmode specifications and synthesis methods. The first part of the report examines the applicability and efficiency of STG's single controller fork-join concurrency ability versus Burstmode's partitioned fork-join concurrency appr...Burstmode circuits; STG1997
16 Myers, Chris J.Covering conditions and algorithms for the synthesis of speed-independent circuitsAbstract-This paper presents theory and algorithms for the synthesis of standard C-implementations of speed-independent circuits. These implementations are block-level circuits which may consist of atomic gates to perform complex functions in order to ensure hazard freedom. First, we present Boolean...1998
17 Harrison, Reid R.; Myers, Chris J.; Schlegel, ChristianAnalog decoding of product codesA design approach is presented for soft-decision decoding of block product codes ("block turbo codes") using analog computation with MOS devices. Application of analog decoding to large code sizes is also considered with the introduction of serial analog interfaces and pipeline schedules.2001-01-11
18 Myers, Chris J.Analog decoding of product codesA design approach is presented for soft-decision decoding of block product codes ("block turbo codes") using analog computation with MOS devices. Application of analog decoding to large code sizes is also considered with the introduction of serial analog interfaces and pipeline schedules.2001
19 Myers, Chris J.An asynchronous implementations of the MAXLIST algorithmABSTRACT We present an efficient asynchronous VLSI architecture for calculating running maximum or minimum values over a sliding window. Running maximums or minimums are very useful for many signal and image processing tasks. Our architecture performs the calculation using the MAXLIST algorithm. In...1997
20 Myers, Chris J.Stochastic cycle period analysis in timed circuitsThis paper presents the stochastic cycle period as a performance metric for timed asynchronous circuits. The stochastic cycle period is a sum of weighted delays whose value represents the expected delay of a single cycle in the specification. Each weight denotes the amount of time a delay contribute...1999
21 Myers, Chris J.Efficient verification of hazard-freedom in gate-level timed asynchronous circuitsAbstract-This paper presents an efficient method for verifying hazard-freedom in gate-level timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that are optimized using explicit timing information. In asynchronous circuits, correct operation requires that there are no ha...2007
22 Stevens, KennethTimed logic conformance and its applicationTimed Logic Conformance _x000B_TLC_x000C_ is a bisimulation-style partial order relationship defined over the statespace of Timed Safety Automata _x000B_TSA_x000C_ with real-valued clocks. In contrast to timed simulation. Calculus of Timed Refine- ment _x000B_CTR_x000C_, and Time-Abstracted bisim...1999
23 Myers, Chris J.Effcient verification of hazard-freedom in gate-level timed asynchronous circuitsThis paper presents an efficient method for verifying hazard freedom in timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that utilize explicit timing information fur optimization throughout the entire design process. In asynchronous circuits, correct operation require...2003
24 Myers, Chris J.Timed circuit verification using TEL structuresAbstract-Recent design examples have shown that significant performance gains are realized when circuit designers are allowed to make aggressive timing assumptions. Circuit correctness in these aggressive styles is highly timing dependent and, in industry, they are typically designed by hand. In ord...2001
25 Brunvand, Erik L.Automatic rapid prototyping of semi-custom VLSI circuits using actel FPGAsAbstract : We describe a technique for translating semi-custom VLSI circuits automatically into field programmable gate arrays (FPGAs) for rapid prototyping to develop a system. Using an array multiplier as an example of this translation, the VLSI circuits are designed using a cell-matrix based envi...1995
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