UScholar Works | Institutional Repository | J. Willard Marriott Digital Library

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		Creator	Title	Description	Subject	Date
1		Balasubramonian, Rajeev	The effect of interconnect design on the performance of large L2 caches	The ever increasing sizes of on-chip caches and the growing domination of wire delay have changed the traditional design approach of the memory hierarchy. Many recent proposals advocate splitting the cache into a large number of banks and employ an on-chip network to allow fast access to nearby ban...		2006
2		Balasubramonian, Rajeev	Exploring the design space for 3D clustered architectures	3D die-stacked chips are emerging as intriguing prospects for the future because of their ability to reduce on-chip wire delays and power consumption. However, they will likely cause an increase in chip operating temperature, which is already a major bottleneck in modern microprocessor design. We...		2006

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