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CreatorTitleDescriptionSubjectDate
1 Carter, John B.Avalanche: A communication and memory architecture for scalable parallel computingAs the gap between processor and memory speeds widens, system designers will inevitably incorporate increasingly deep memory hierarchies to maintain the balance between processor and memory system performance. At the same time, most communication subsystems are permitted access only to main memory ...Avalanche; Computer memory; Memory architecture1995
2 Weinstein, DavidCache-rings for memory efficient isosurface constructionProcessor speeds continue to increase at faster rates than memory speeds. As this performance gap widens, it becomes increasingly important to develop "memory-conscious" algorithms - programs that still optimize instruction count and algorithmic complexity, but that also integrate optimizations for ...Processor speeds; Memory speeds; Computer memory; Cache-rings1997
3 Chatterjee, Prosenjit; Gopalakrishnan, GaneshFormally specifying memory consistency models and automatically generating executable specificationsMemory ordering properties of shared memory multiprocessors are more subtle and less well understood than cache coherence. These properties tend to be processor or platform specific and are not always formally specified. It is difficult to compare even those platforms whose memory ordering propert...Computer memory; Memory consistency models; Memory ordering; Shared memory multiprocessors2001
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