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 | Balasubramonian, Rajeev | Leveraging wire properties at the microarchitecture level | In future microprocessors, communication will emerge as a major bottleneck. The authors advocate composing future interconnects of some wires that minimize latency, some that maximize bandwidth, and some that minimize power. A microarchitecture aware of these wire characteristics can steer on-chip ... | Microarchitecture; Interconnects; Cache coherence | 2006-11 |
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