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 | Balasubramonian, Rajeev | Architecting efficient interconnects for large caches with CACTI 6.0 | Efficiently executing multithreaded applications on future multicores will require fast intercore communication. Most of this communication happens via reads and writes to large shared caches in the memory hierarchy. Microprocessor performance and power will be strongly influenced by the long inter... | Interconnects; CACTI 6.0; Non-uniform cache architectures (NUCA) | 2008-01 |
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