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| Creator | Title | Description | Subject | Date | ||
|---|---|---|---|---|---|---|
| 1 |
 | Balasubramonian, Rajeev | Architecting efficient interconnects for large caches with CACTI 6.0 | Efficiently executing multithreaded applications on future multicores will require fast intercore communication. Most of this communication happens via reads and writes to large shared caches in the memory hierarchy. Microprocessor performance and power will be strongly influenced by the long inter... | Interconnects; CACTI 6.0; Non-uniform cache architectures (NUCA) | 2008-01 |
| 2 |
 | Balasubramonian, Rajeev | Leveraging wire properties at the microarchitecture level | In future microprocessors, communication will emerge as a major bottleneck. The authors advocate composing future interconnects of some wires that minimize latency, some that maximize bandwidth, and some that minimize power. A microarchitecture aware of these wire characteristics can steer on-chip ... | Microarchitecture; Interconnects; Cache coherence | 2006-11 |
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