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| Creator | Title | Description | Subject | Date | ||
|---|---|---|---|---|---|---|
| 1 |
 | Gopalakrishnan, Ganesh | Towards a verification technique for large synchronous circuits | We present a symbolic simulation based veri cation approach which can be applied to large synchronous circuits A new technique to encode the state and input constraints as parametric Boolean expressions over the state and input variables is used to make our symbolic simulation based veri cation... | symbolic simulation; verification | 1992 |
| 2 |
 | Gopalakrishnan, Ganesh | Towards a verification technique for large synchronous circuits | We present a symbolic simulation based verification approach which can be applied to large synchronous circuits. A new technique to encode the state and input constraints as parametric Boolean expressions over the state and input variables is used to make our symbolic simulation based verification... | Verification; symbolic simulation | 1992 |
| 3 |
 | Gopalakrishnan, Ganesh | Verification of regular arrays by symbolic simulation | Many algorithms have an efficient hardware formulation as a regular array of cells, which can be implemented in VLSI as regular circuit structures. Bit-sliced microprocessors, pattern matching circuits, associative cache memories, Hue-grain systolic arrays, and embedded memory-with-logic structure... | Verification; regular arrays; symbolic simulation | 1991 |
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