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| Creator | Title | Description | Subject | Date | ||
|---|---|---|---|---|---|---|
| 1 |
 | Gopalakrishnan, Ganesh | Dynamic reordering of high latency transactions in time-warp simulation using a modified micropipeline | Time warp based simulation of discrete-event systems is an efficient way to overcome the synchronization overhead during distributed simulation. As computations may proceed beyond synchronization barriers in time warp, multiple checkpoints of state need to be maintained to be able to rollback inva... | Asynchronous design; Micropipelines; Dynamic instruction reordering; Time warp simulations | 1992 |
| 2 |
 | Richardson, William F.; Brunvand, Erik L. | The NSR processor prototype | The NSR Non Synchronous RISC processor is a general purpose processor structured as a collection of self timed units that operate concurrently and communicate over bundled data channels in the style of micropipelines?? These units correspond to standard synchronous pipeline stages such as Instr... | Self-timed Systems; Asynchronous systems; Micropipelines; FPGAs; RISC processor | 1992 |
| 3 |
 | Richardson, William F.; Brunvand, Erik L. | The NSR processor prototype | The NSR (Non-Synchronous RISC) processor is a general purpose processor structured as a collection of self-timed units that operate concurrently and communicate over bundled data channels in the style of micropipelines. These units correspond to standard synchronous pipeline stages such as Instructi... | Self-timed Systems; Asynchronous systems; Micropipelines; FPGAs; RISC processor; NSR | 1992 |
| 4 |
 | Gopalakrishnan, Ganesh | Some unusual micropipeline circuits | We present a few unusual Micropipelines (Sutherland, CACM, September 1989) that employ the Muller C-ELEMENT or an extension of the C-ELEMENT called LOCKC (Liebchen and Gopalakrishnan, ICCD, 1992). We first describe two variations of the two-dimensional Micropipeline structure realized using ordinary... | Micropipeline circuits; Micropipelines | 1993 |
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